Searched refs:DDR1 (Results 1 – 9 of 9) sorted by relevance
33 DDR1: 0x80000000 - 0xBFFFFFFF49 For the areas that reside within DDR1 they must not be used prior to s_init()
24 lpddr2_config_iomux(DDR1); in setup_iomux_ddr()
42 case DDR1: in lpddr2_config_iomux()
11 #define DDR1 1 macro
33 - bit 1: DDR1
130 bool "Freescale DDR1 controller"
67 /* Dummy clock for pll11 (DDR1) until actually implemented */
7 per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
425 Freescale DDR1 controller.440 Board config to use DDR1. It can be enabled for SoCs with441 Freescale DDR1 or DDR2 controllers, depending on the board