1*4882a593SmuzhiyunOverview of SPL on OMAP3 devices 2*4882a593Smuzhiyun================================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunIntroduction 5*4882a593Smuzhiyun------------ 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThis document provides an overview of how SPL functions on OMAP3 (and related 8*4882a593Smuzhiyunsuch as am35x and am37x) processors. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunMethodology 11*4882a593Smuzhiyun----------- 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunOn these platforms the ROM supports trying a sequence of boot devices. Once 14*4882a593Smuzhiyunone has been used successfully to load SPL this information is stored in memory 15*4882a593Smuzhiyunand the location stored in a register. We will read this to determine where to 16*4882a593Smuzhiyunread U-Boot from in turn. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunMemory Map 19*4882a593Smuzhiyun---------- 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunThis is an example of a typical setup. See top-level README for documentation 22*4882a593Smuzhiyunof which CONFIG variables control these values. For a given board and the 23*4882a593Smuzhiyunamount of DRAM available to it different values may need to be used. 24*4882a593SmuzhiyunNote that the size of the SPL text rodata and data is enforced with a CONFIG 25*4882a593Smuzhiyunoption and growing over that size results in a link error. The SPL stack 26*4882a593Smuzhiyunstarts at the top of SRAM (which is configurable) and grows downward. The 27*4882a593Smuzhiyunspace between the top of SRAM and the enforced upper bound on the size of the 28*4882a593SmuzhiyunSPL text, data and rodata is considered the safe stack area. Details on 29*4882a593Smuzhiyunconfirming this behavior are shown below. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunA portion of the system memory map looks as follows: 32*4882a593SmuzhiyunSRAM: 0x40200000 - 0x4020FFFF 33*4882a593SmuzhiyunDDR1: 0x80000000 - 0xBFFFFFFF 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunOption 1 (SPL only): 36*4882a593Smuzhiyun0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata 37*4882a593Smuzhiyun0x4020E000 - 0x4020FFFC: Area for the SPL stack. 38*4882a593Smuzhiyun0x80000000 - 0x8007FFFF: Area for the SPL BSS. 39*4882a593Smuzhiyun0x80100000: CONFIG_SYS_TEXT_BASE of U-Boot 40*4882a593Smuzhiyun0x80208000 - 0x80307FFF: malloc() pool available to SPL. 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunOption 2 (SPL or X-Loader): 43*4882a593Smuzhiyun0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata 44*4882a593Smuzhiyun0x4020E000 - 0x4020FFFC: Area for the SPL stack. 45*4882a593Smuzhiyun0x80008000: CONFIG_SYS_TEXT_BASE of U-Boot 46*4882a593Smuzhiyun0x87000000 - 0x8707FFFF: Area for the SPL BSS. 47*4882a593Smuzhiyun0x87080000 - 0x870FFFFF: malloc() pool available to SPL. 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunFor the areas that reside within DDR1 they must not be used prior to s_init() 50*4882a593Smuzhiyuncompleting. Note that CONFIG_SYS_TEXT_BASE must be clear of the areas that SPL 51*4882a593Smuzhiyunuses while running. This is why we have two versions of the memory map that 52*4882a593Smuzhiyunonly vary in where the BSS and malloc pool reside. 53