Searched refs:CLK_RST_XUSBIO_PLL_CFG0 (Results 1 – 1 of 1) sorted by relevance
209 #define CLK_RST_XUSBIO_PLL_CFG0 0x51c macro370 value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()375 writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()391 value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()393 writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0); in pcie_phy_enable()