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| H A D | plat_helpers.S | fe87637a25168ea25b9ff869882a66c54287de5f Mon Jul 12 10:12:09 UTC 2021 Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> fix(rcar3): clear TCR_EL1 at the BL2 entry point
According to ARM DDI0601 2025-06 [1] TCR_EL1, Translation Control
Register (EL1), all fields of TCR_EL1 do, on a Warm reset, (this
field) resets to an architecturally UNKNOWN value.
On some SoCs, after reset, this TCR_EL1 may not be 0, which in itself
is perfectly valid behavior. However, existing software may depend on
TCR_EL1 being 0, and the UNKNOWN value may confuse such software.
Reset TCR_EL1 to well defined value 0 at BL2 entrypoint to achieve
maximum compatibility.
[1] https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/TCR-EL1--Translation-Control-Register--EL1-
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # update commit message
Change-Id: If3a1d40291b9b9768a8fc55e750bd742f3cc4ddc
---
Note: This is related to MR 25532 , but with reworked commit message
and broken out from the large work-in-progress series.
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