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| /optee_os/core/arch/riscv/mm/ |
| H A D | sub.mk | f7e4fc1e3c341532465a8e0c602e77d1cc7a3633 Mon Jun 12 13:06:35 UTC 2023 Marouene Boubakri <marouene.boubakri@nxp.com> riscv: mm: initial implementation of memory management routines
An initial working implementation of mm for RISC-V MMU-enabled harts.
The default MMU mode is set to Sv39 for RV64 with 3 page table levels.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| H A D | core_mmu_arch.c | f7e4fc1e3c341532465a8e0c602e77d1cc7a3633 Mon Jun 12 13:06:35 UTC 2023 Marouene Boubakri <marouene.boubakri@nxp.com> riscv: mm: initial implementation of memory management routines
An initial working implementation of mm for RISC-V MMU-enabled harts.
The default MMU mode is set to Sv39 for RV64 with 3 page table levels.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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