| #
f7e4fc1e |
| 12-Jun-2023 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
riscv: mm: initial implementation of memory management routines
An initial working implementation of mm for RISC-V MMU-enabled harts.
The default MMU mode is set to Sv39 for RV64 with 3 page table l
riscv: mm: initial implementation of memory management routines
An initial working implementation of mm for RISC-V MMU-enabled harts.
The default MMU mode is set to Sv39 for RV64 with 3 page table levels.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| #
cabb8df3 |
| 20-Jun-2023 |
Alvin Chang <alvinga@andestech.com> |
core: riscv: Add cflags for excluding source files from ftrace
Some C source files may lead to incorrect behaviors in ftrace. Exclude
them when the system is compiled with ftrace support.
Signed-of
core: riscv: Add cflags for excluding source files from ftrace
Some C source files may lead to incorrect behaviors in ftrace. Exclude
them when the system is compiled with ftrace support.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
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| #
2f39a4c2 |
| 02-Nov-2022 |
Marouene Boubakri <marouene.boubakri@nxp.com> |
riscv: mm: tlb_helpers_rv.S: translation look-aside buffer invalidate
Implement tlbi_all(), tlbi_mva_allasid() and tlbi_asid() using supervisor
memory-management fence instruction SFENCE.VMA.
Signe
riscv: mm: tlb_helpers_rv.S: translation look-aside buffer invalidate
Implement tlbi_all(), tlbi_mva_allasid() and tlbi_asid() using supervisor
memory-management fence instruction SFENCE.VMA.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
show more ...
|