Searched hist:ef653d93ccd6ba1888c61706469021fc623c3318 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/bl31/aarch64/ |
| H A D | runtime_exceptions.S | ef653d93ccd6ba1888c61706469021fc623c3318 Wed Nov 29 16:59:34 UTC 2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com> AArch64: Refactor GP register restore to separate function
At present, the function that restores general purpose registers also
does ERET. Refactor the restore code to restore general purpose
registers without ERET to complement the save function.
The macro save_x18_to_x29_sp_el0 was used only once, and is therefore
removed, and its contents expanded inline for readability.
No functional changes, but with this patch:
- The SMC return path will incur an branch-return and an additional
register load.
- The unknown SMC path restores registers x0 to x3.
Change-Id: I7a1a63e17f34f9cde810685d70a0ad13ca3b7c50
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context.S | ef653d93ccd6ba1888c61706469021fc623c3318 Wed Nov 29 16:59:34 UTC 2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com> AArch64: Refactor GP register restore to separate function
At present, the function that restores general purpose registers also
does ERET. Refactor the restore code to restore general purpose
registers without ERET to complement the save function.
The macro save_x18_to_x29_sp_el0 was used only once, and is therefore
removed, and its contents expanded inline for readability.
No functional changes, but with this patch:
- The SMC return path will incur an branch-return and an additional
register load.
- The unknown SMC path restores registers x0 to x3.
Change-Id: I7a1a63e17f34f9cde810685d70a0ad13ca3b7c50
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
|