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| H A D | clk_rk3399.c | e78991bff6c180cd013fbf57297d2e2e3ffb1bd2 Wed Sep 20 06:38:58 UTC 2017 David Wu <david.wu@rock-chips.com> rockchip: clk: Add rk3399 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.
Change-Id: Ifff2c9716ea409eee76cbeaf0a0878df05f304d2
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit 364fc7315aa0e6e20f604bb8b369b4bdc0dd8e8a)
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