Searched hist:de8b9cedccd652c357aff5311f8d7cb9d663514b (Results 1 – 2 of 2) sorted by relevance
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| H A D | tc_helpers.S | de8b9cedccd652c357aff5311f8d7cb9d663514b Wed Jul 17 14:34:28 UTC 2024 Jagdish Gediya <jagdish.gediya@arm.com> feat(tc): enable el1 access to DSU PMU registers
DSU PMU registers are write accessible in EL1 if the ACTLR_EL3[12] bit
and the ACTLR_EL2[12] bit are set to 1, and these registers are need to
be set for all cores, so set these bits in platform reset handler.
Change-Id: I1db6915939727f0909c05c8b103e37984aadb443
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
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| H A D | platform_def.h | de8b9cedccd652c357aff5311f8d7cb9d663514b Wed Jul 17 14:34:28 UTC 2024 Jagdish Gediya <jagdish.gediya@arm.com> feat(tc): enable el1 access to DSU PMU registers
DSU PMU registers are write accessible in EL1 if the ACTLR_EL3[12] bit
and the ACTLR_EL2[12] bit are set to 1, and these registers are need to
be set for all cores, so set these bits in platform reset handler.
Change-Id: I1db6915939727f0909c05c8b103e37984aadb443
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
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