Searched hist:dc57f5a0e8f3b502fc958bc64a5ec0b0f46ef11a (Results 1 – 5 of 5) sorted by relevance
| /optee_os/core/arch/arm/plat-zynqmp/ |
| H A D | sub.mk | dc57f5a0e8f3b502fc958bc64a5ec0b0f46ef11a Sun Nov 15 19:05:18 UTC 2015 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for ZynqMP
Add support for Xilinx UltraScale+ Zynq MPSoC.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| H A D | platform_config.h | dc57f5a0e8f3b502fc958bc64a5ec0b0f46ef11a Sun Nov 15 19:05:18 UTC 2015 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for ZynqMP
Add support for Xilinx UltraScale+ Zynq MPSoC.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | conf.mk | dc57f5a0e8f3b502fc958bc64a5ec0b0f46ef11a Sun Nov 15 19:05:18 UTC 2015 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for ZynqMP
Add support for Xilinx UltraScale+ Zynq MPSoC.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | main.c | dc57f5a0e8f3b502fc958bc64a5ec0b0f46ef11a Sun Nov 15 19:05:18 UTC 2015 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for ZynqMP
Add support for Xilinx UltraScale+ Zynq MPSoC.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/ |
| H A D | README.md | dc57f5a0e8f3b502fc958bc64a5ec0b0f46ef11a Sun Nov 15 19:05:18 UTC 2015 Soren Brinkmann <soren.brinkmann@xilinx.com> Add support for ZynqMP
Add support for Xilinx UltraScale+ Zynq MPSoC.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|