Searched hist:cf82aff09801e3f66dc355faa434dae83e031cba (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/common/ |
| H A D | socfpga_psci.c | cf82aff09801e3f66dc355faa434dae83e031cba Tue Oct 22 05:39:14 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: Modify BL31 address mapping
Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use
of On-Chip RAM for BL31 specific variables filling down from handoff
offset to reduce fragmentation
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099
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| /rk3399_ARM-atf/plat/intel/soc/common/include/ |
| H A D | platform_def.h | cf82aff09801e3f66dc355faa434dae83e031cba Tue Oct 22 05:39:14 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: Modify BL31 address mapping
Load BL31 to DDR instead of On-Chip RAM for scalability. Also, make use
of On-Chip RAM for BL31 specific variables filling down from handoff
offset to reduce fragmentation
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib64f48bd14f71e5fca2d406f4ede3386f2881099
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