Searched hist:cb2702c4b72746b6ef4e2da8d04d3f4b56d85398 (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a710.S | cb2702c4b72746b6ef4e2da8d04d3f4b56d85398 Mon Jun 09 22:06:55 UTC 2025 John Powell <john.powell@arm.com> fix(cpus): workaround for Cortex-A710 erratum 1927200
Cortex-A710 erratum 1927200 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.
The fix is to insert DMB ST before acquire atomic instructions
without release semantics via instruction patching.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101
Change-Id: I53c4aa17c1c2dc85b68f17d58f93bb1ee6b3d488
Signed-off-by: John Powell <john.powell@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | cb2702c4b72746b6ef4e2da8d04d3f4b56d85398 Mon Jun 09 22:06:55 UTC 2025 John Powell <john.powell@arm.com> fix(cpus): workaround for Cortex-A710 erratum 1927200
Cortex-A710 erratum 1927200 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.
The fix is to insert DMB ST before acquire atomic instructions
without release semantics via instruction patching.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101
Change-Id: I53c4aa17c1c2dc85b68f17d58f93bb1ee6b3d488
Signed-off-by: John Powell <john.powell@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | cb2702c4b72746b6ef4e2da8d04d3f4b56d85398 Mon Jun 09 22:06:55 UTC 2025 John Powell <john.powell@arm.com> fix(cpus): workaround for Cortex-A710 erratum 1927200
Cortex-A710 erratum 1927200 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.
The fix is to insert DMB ST before acquire atomic instructions
without release semantics via instruction patching.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101
Change-Id: I53c4aa17c1c2dc85b68f17d58f93bb1ee6b3d488
Signed-off-by: John Powell <john.powell@arm.com>
|