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| H A D | plat_ipi.h | c96f838acb4825c71e534af4f327dec61a7bfd79 Wed Oct 01 09:33:22 UTC 2025 Devanshi Chauhan <devanshi.chauhan@amd.com> fix(versal): modify IPI4 and IPI5 trigger bit definitions
The IPI4 and IPI5 trigger bit definitions are incorrect according
to the register database specification. This discrepancy can
cause IPI communication failures between processing units in
Versal SoCs. So, modified the trigger bits to align the software
definitions with the hardware register specification as documented
in the register database.
Change-Id: I1e32961124daf8e5635906fb615e98a650130f27
Signed-off-by: Devanshi Chauhan <devanshi.chauhan@amd.com>
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