Searched hist:b42192bcbdbe9fab4aadca903cac2f928a1d7154 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/nvidia/tegra/common/aarch64/ |
| H A D | tegra_helpers.S | b42192bcbdbe9fab4aadca903cac2f928a1d7154 Fri Aug 21 10:26:02 UTC 2015 Varun Wadekar <vwadekar@nvidia.com> Tegra210: wait for 512 timer ticks before retention entry
This patch programs the CPUECTLR_EL1 and L2ECTLR_EL1 registers,
so that the core waits for 512 generic timer CNTVALUEB ticks before
entering retention state, after executing a WFI instruction.
This functionality is configurable and can be enabled for platforms
by setting the newly defined 'ENABLE_L2_DYNAMIC_RETENTION' and
'ENABLE_CPU_DYNAMIC_RETENTION' flag.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|
| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t210/ |
| H A D | platform_t210.mk | b42192bcbdbe9fab4aadca903cac2f928a1d7154 Fri Aug 21 10:26:02 UTC 2015 Varun Wadekar <vwadekar@nvidia.com> Tegra210: wait for 512 timer ticks before retention entry
This patch programs the CPUECTLR_EL1 and L2ECTLR_EL1 registers,
so that the core waits for 512 generic timer CNTVALUEB ticks before
entering retention state, after executing a WFI instruction.
This functionality is configurable and can be enabled for platforms
by setting the newly defined 'ENABLE_L2_DYNAMIC_RETENTION' and
'ENABLE_CPU_DYNAMIC_RETENTION' flag.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|