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/optee_os/core/drivers/clk/sam/
H A Dclk-sam9x60-pll.cb20bd0e0d0bb88b66a85e8fd75e52acca58a3eb8 Thu Jan 23 03:08:17 UTC 2025 Tony Han <tony.han@microchip.com> drivers: clk: sam: fix underflow of the divider for sama7g5 PLL clocks

Fix the underflow of the divider calculated when clock given rate is
greater than the rate of the clock parent.

Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>