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| H A D | clk_rk3328.c | ae74d3d5ad3cffadf8908d726eb8f5e7d70126d4 Wed Sep 20 06:35:44 UTC 2017 David Wu <david.wu@rock-chips.com> rockchip: clk: Add rk3328 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Change-Id: I73608db35c926470692eb982e881b01e52fcf2d9
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
(cherry picked from commit b375d84135e26d5ec5034a515af4df5981785f37)
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