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/optee_os/core/arch/arm/plat-zynq7k/
H A Dplat_init.Sa0c170d098db04249bb70b88d62ddd1d53101ca3 Tue Mar 14 14:42:57 UTC 2017 Etienne Carriere <etienne.carriere@linaro.org> plat-zynq7k: fix NSACR initialization

Bits #9..#0 of CPU register NSACR are specified by ARM as SBZP ("Set
Bit to Zero or Preserve on write"). This change fixes plat-zynq7k to
conform with the specs.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>