Searched hist:a00dfa042d3eecbe96308d87f38710e79a29e00c (Results 1 – 1 of 1) sorted by relevance
| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3368.c | a00dfa042d3eecbe96308d87f38710e79a29e00c Thu Jun 22 22:01:10 UTC 2017 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> rockchip: clk: rk3368: implement DPLL (DRAM PLL) support
To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).
This commit implements setting the DPLL (CLK_DDR) and provides PLL
configuration details for the common DRAM operating speeds found on
RK3368 boards.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
|