Searched hist:"92 d22776fc15e8301e1c3f2689a1f04143e5db30" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/agilex5/include/ |
| H A D | agilex5_iossm_mailbox.h | 92d22776fc15e8301e1c3f2689a1f04143e5db30 Wed Mar 19 04:34:35 UTC 2025 Girisha Dengi <girisha.dengi@intel.com> fix(intel): support DDR In-line and Out-of-Band ECC handling
Enable the DDR ECC feature, initialize the memory based on
the ECC type (in-line or out-of-band), detect the DBE errors
and recover the system accordingly.
Change-Id: I5138124e0d68dc8c93c98ae71eb13a77e49fd682
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|
| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_iossm_mailbox.c | 92d22776fc15e8301e1c3f2689a1f04143e5db30 Wed Mar 19 04:34:35 UTC 2025 Girisha Dengi <girisha.dengi@intel.com> fix(intel): support DDR In-line and Out-of-Band ECC handling
Enable the DDR ECC feature, initialize the memory based on
the ECC type (in-line or out-of-band), detect the DBE errors
and recover the system accordingly.
Change-Id: I5138124e0d68dc8c93c98ae71eb13a77e49fd682
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|
| H A D | agilex5_ddr.c | 92d22776fc15e8301e1c3f2689a1f04143e5db30 Wed Mar 19 04:34:35 UTC 2025 Girisha Dengi <girisha.dengi@intel.com> fix(intel): support DDR In-line and Out-of-Band ECC handling
Enable the DDR ECC feature, initialize the memory based on
the ECC type (in-line or out-of-band), detect the DBE errors
and recover the system accordingly.
Change-Id: I5138124e0d68dc8c93c98ae71eb13a77e49fd682
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
|