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/rk3399_ARM-atf/plat/nvidia/tegra/include/
H A Dplat_macros.S8510376c26449b45973821f226d180c19a30a1e0 Tue Jan 02 22:10:18 UTC 2018 Varun Wadekar <vwadekar@nvidia.com> Tegra: fix offset used to dump GICD registers from crash handler

The GICD registers are 32-bits wide whereas the crash handler was reading
them as 64-bit ones. This patch fixes the code to read the GICD registers,
32-bits at a time, from the paltform's crash handler.

Change-Id: If3d6608529684ecc02be6a1b715012310813b2a4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>