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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rv1126.c | 82c18007fbc0e1d1afb3bfdcdc597dba58c6476b Mon Apr 13 13:03:52 UTC 2020 Finley Xiao <finley.xiao@rock-chips.com> clk: rockchip: rv1126: Modify divs for pll
There are some constraints for pll.
Input frequency range(Int): 5MHz to 1200MHz.
Input frequency range(Frac): 10MHz to 1200MHz.
Output frequency range: 16MHz to 6400MHz.
VCO frequency range: 1600MHz to 6400MHz.
Feedback divide(Int): 16 t0 640.
Feedback divide(Frac): 20 to 320.
Postdiv1 >= Postdiv2.
Change-Id: Ic8b8da6097f476597733984145056b6cc6cc453e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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