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/rk3399_ARM-atf/include/lib/cpus/aarch32/
H A Dcortex_a72.h81858a353f8e45f5cc57ce855188043b1745ea08 Tue Jan 10 19:25:42 UTC 2023 Andrew Davis <afd@ti.com> feat(ti): set L2 cache ECC and and parity on A72 cores

The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Icd00bc4aa9c1c48f0fb2a10ea66e75e0b146ef3c
/rk3399_ARM-atf/include/lib/cpus/aarch64/
H A Dcortex_a72.h81858a353f8e45f5cc57ce855188043b1745ea08 Tue Jan 10 19:25:42 UTC 2023 Andrew Davis <afd@ti.com> feat(ti): set L2 cache ECC and and parity on A72 cores

The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Icd00bc4aa9c1c48f0fb2a10ea66e75e0b146ef3c