Searched hist:"7 f9e9e4b40152c0cb52bcc53ac3d32fd1c978416" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/common/include/ |
| H A D | socfpga_system_manager.h | 7f9e9e4b40152c0cb52bcc53ac3d32fd1c978416 Fri Aug 19 11:40:17 UTC 2022 Jit Loon Lim <jit.loon.lim@intel.com> fix(intel): mailbox store QSPI ref clk in scratch reg
When HPS requests QSPI controller access the SDM returns the QSPI
reference clock frequency. Store the provided reference clock frequency
(in kHz) in BOOT_SCRATCH_COLD_0 register (bits [27:0]) as u-boot
QSPI driver expects this.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6b95c19db602387a79ff10abdebbc57abb0c07ff
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| /rk3399_ARM-atf/plat/intel/soc/common/soc/ |
| H A D | socfpga_mailbox.c | 7f9e9e4b40152c0cb52bcc53ac3d32fd1c978416 Fri Aug 19 11:40:17 UTC 2022 Jit Loon Lim <jit.loon.lim@intel.com> fix(intel): mailbox store QSPI ref clk in scratch reg
When HPS requests QSPI controller access the SDM returns the QSPI
reference clock frequency. Store the provided reference clock frequency
(in kHz) in BOOT_SCRATCH_COLD_0 register (bits [27:0]) as u-boot
QSPI driver expects this.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6b95c19db602387a79ff10abdebbc57abb0c07ff
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