Searched hist:"66 a7752834382595d26214783ae4698fd1f00bd6" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/marvell/armada/a3k/common/include/ |
| H A D | platform_def.h | 66a7752834382595d26214783ae4698fd1f00bd6 Thu May 13 12:53:44 UTC 2021 Pali Rohár <pali@kernel.org> fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation
UART parent clock is by default the platform's xtal clock, which is
25 MHz.
The value defined in the driver, though, is 25.8048 MHz. This is a hack
for the suboptimal divisor calculation
Divisor = UART clock / (16 * baudrate)
which does not use rounding division, resulting in a suboptimal value
for divisor if the correct parent clock rate was used.
Change the code for divisor calculation to
Divisor = Round(UART clock / (16 * baudrate))
and change the parent clock rate value to 25 MHz.
The final UART divisor for default baudrate 115200 is not affected by
this change.
(Note that the parent clock rate should not be defined via a macro,
since the xtal clock can also be 40 MHz. This is outside of the scope of
this fix, though.)
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
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| /rk3399_ARM-atf/drivers/marvell/uart/ |
| H A D | a3700_console.S | 66a7752834382595d26214783ae4698fd1f00bd6 Thu May 13 12:53:44 UTC 2021 Pali Rohár <pali@kernel.org> fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation
UART parent clock is by default the platform's xtal clock, which is
25 MHz.
The value defined in the driver, though, is 25.8048 MHz. This is a hack
for the suboptimal divisor calculation
Divisor = UART clock / (16 * baudrate)
which does not use rounding division, resulting in a suboptimal value
for divisor if the correct parent clock rate was used.
Change the code for divisor calculation to
Divisor = Round(UART clock / (16 * baudrate))
and change the parent clock rate value to 25 MHz.
The final UART divisor for default baudrate 115200 is not affected by
this change.
(Note that the parent clock rate should not be defined via a macro,
since the xtal clock can also be 40 MHz. This is outside of the scope of
this fix, though.)
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
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