Searched hist:"6454758 b1b2cd941e86b86061d2a7c898ee81ed3" (Results 1 – 3 of 3) sorted by relevance
| /optee_os/core/arch/riscv/kernel/ |
| H A D | tee_time_rdtime.c | 6454758b1b2cd941e86b86061d2a7c898ee81ed3 Thu Dec 01 12:57:20 UTC 2022 Marouene Boubakri <marouene.boubakri@nxp.com> core: riscv: add time source based on time registers
Implement a TEE time source based on CSR_TIME and CSR_HTIME for S-Mode
and CLINT MTIME register for M-Mode.
CFG_RISCV_TIME_SOURCE_RDTIME flag to enable or not building the time
source. CFG_RISCV_MTIME_RATE defines the timer rate, default to 10MHz.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| H A D | sub.mk | 6454758b1b2cd941e86b86061d2a7c898ee81ed3 Thu Dec 01 12:57:20 UTC 2022 Marouene Boubakri <marouene.boubakri@nxp.com> core: riscv: add time source based on time registers
Implement a TEE time source based on CSR_TIME and CSR_HTIME for S-Mode
and CLINT MTIME register for M-Mode.
CFG_RISCV_TIME_SOURCE_RDTIME flag to enable or not building the time
source. CFG_RISCV_MTIME_RATE defines the timer rate, default to 10MHz.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/arch/riscv/plat-spike/ |
| H A D | conf.mk | 6454758b1b2cd941e86b86061d2a7c898ee81ed3 Thu Dec 01 12:57:20 UTC 2022 Marouene Boubakri <marouene.boubakri@nxp.com> core: riscv: add time source based on time registers
Implement a TEE time source based on CSR_TIME and CSR_HTIME for S-Mode
and CLINT MTIME register for M-Mode.
CFG_RISCV_TIME_SOURCE_RDTIME flag to enable or not building the time
source. CFG_RISCV_MTIME_RATE defines the timer rate, default to 10MHz.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|