Searched hist:"57356 e9094ac5ecbca29131a3c53c6978457350f" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/bl32/tsp/aarch64/ |
| H A D | tsp_exceptions.S | 57356e9094ac5ecbca29131a3c53c6978457350f Fri May 09 11:17:56 UTC 2014 Achin Gupta <achin.gupta@arm.com> Add support for asynchronous FIQ handling in TSP
This patch adds support in the TSP to handle FIQ interrupts that are
generated when execution is in the TSP. S-EL1 interrupt are handled
normally and execution resumes at the instruction where the exception
was originally taken. S-EL3 interrupts i.e. any interrupt not
recognized by the TSP are handed to the TSPD. Execution resumes
normally once such an interrupt has been handled at EL3.
Change-Id: Ia3ada9a4fb15670afcc12538a6456f21efe58a8f
|
| H A D | tsp_entrypoint.S | 57356e9094ac5ecbca29131a3c53c6978457350f Fri May 09 11:17:56 UTC 2014 Achin Gupta <achin.gupta@arm.com> Add support for asynchronous FIQ handling in TSP
This patch adds support in the TSP to handle FIQ interrupts that are
generated when execution is in the TSP. S-EL1 interrupt are handled
normally and execution resumes at the instruction where the exception
was originally taken. S-EL3 interrupts i.e. any interrupt not
recognized by the TSP are handed to the TSPD. Execution resumes
normally once such an interrupt has been handled at EL3.
Change-Id: Ia3ada9a4fb15670afcc12538a6456f21efe58a8f
|
| /rk3399_ARM-atf/bl32/tsp/ |
| H A D | tsp.mk | 57356e9094ac5ecbca29131a3c53c6978457350f Fri May 09 11:17:56 UTC 2014 Achin Gupta <achin.gupta@arm.com> Add support for asynchronous FIQ handling in TSP
This patch adds support in the TSP to handle FIQ interrupts that are
generated when execution is in the TSP. S-EL1 interrupt are handled
normally and execution resumes at the instruction where the exception
was originally taken. S-EL3 interrupts i.e. any interrupt not
recognized by the TSP are handed to the TSPD. Execution resumes
normally once such an interrupt has been handled at EL3.
Change-Id: Ia3ada9a4fb15670afcc12538a6456f21efe58a8f
|