Searched hist:"4 f690ae4c4edd96d4a66f8125fa90298c54081e5" (Results 1 – 2 of 2) sorted by relevance
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| H A D | RK3288MINIALL.ini | 4f690ae4c4edd96d4a66f8125fa90298c54081e5 Thu Jan 14 08:26:17 UTC 2016 Hecanyang <hcy@rock-chips.com> ddr: ddr update to 20151202 version.
ddr init code print version is : DDR Version 1.00 20151202
this version update below features:
1)support use only one channel.
the only channel MUST connect to DDR0
2)support use 3GB total capabilty, include
(I) DDR0:768MB/CS0 + 768MB/CS1
DDR1:768MB/CS0 + 768MB/CS1
(II) DDR0:1.5GB
DDR1:1.5GB
(III)DDR0:2GB
DDR1:1GB
3)fixed ZQ command can't send to 2 rank at the same time
Change-Id: I4e03be591324df574bd9f57ad0ba22ecf50dcd4f
Signed-off-by: Hecanyang <hcy@rock-chips.com>
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| H A D | RK3288.ini | 4f690ae4c4edd96d4a66f8125fa90298c54081e5 Thu Jan 14 08:26:17 UTC 2016 Hecanyang <hcy@rock-chips.com> ddr: ddr update to 20151202 version.
ddr init code print version is : DDR Version 1.00 20151202
this version update below features:
1)support use only one channel.
the only channel MUST connect to DDR0
2)support use 3GB total capabilty, include
(I) DDR0:768MB/CS0 + 768MB/CS1
DDR1:768MB/CS0 + 768MB/CS1
(II) DDR0:1.5GB
DDR1:1.5GB
(III)DDR0:2GB
DDR1:1GB
3)fixed ZQ command can't send to 2 rank at the same time
Change-Id: I4e03be591324df574bd9f57ad0ba22ecf50dcd4f
Signed-off-by: Hecanyang <hcy@rock-chips.com>
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