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/rk3399_rockchip-uboot/board/ge/bx50v3/
H A Dbx50v3.c494d43ec35ff3d27926ed9d668e0df4b7e6ae6d3 Tue Apr 12 22:13:58 UTC 2016 Akshay Bhat <akshay.bhat@timesys.com> board: ge: bx50v3: Setup LDB_DI_CLK source

To generate accurate pixel clocks required by the displays we need to
set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since
PLL5 is disabled on reset, we need to enable PLL5.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>