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| H A D | clk-stm32mp2.c | 40d0cebe1022da24ebbd9ee67b5cdc7049aeaf5e Mon Sep 23 09:57:29 UTC 2024 Patrick Delaunay <patrick.delaunay@foss.st.com> fix(st-clock): force ARM_DIVSEL for flexgen63 config at 400MHz
The clkext2f frequency at 400MHZ, the default flexgen63 config,
is not supported without a divider by 2 as described in reference Manuel,
chapter 3.3 Cortex-A35 clocking:
The clock for the Cortex-A35 subsystem can be selected among:
a clock from the device clock generator (aka ck_cpu1_ext2f). The maximum
frequency on this clock is 400 MHz with a divider by two, enabled thanks
to the CA35SS_SSC_CHGCLKREQ SSC register.
In OpenSTLinux clock tree you assume flexgen63 = 400MHz,
so we force divider by 2 for ck_cpu1_ext2f clock, the CA35 bypass clock
with ARM_DIVSEL = 0.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I9d11f9316ce3a2c7280a9bb7652d241b164ce5a1
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