Searched hist:"1 b1a3eb1edff99b49bb40ad4172073d04a230938" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/agilex5/include/ |
| H A D | agilex5_clock_manager.h | 1b1a3eb1edff99b49bb40ad4172073d04a230938 Wed May 17 04:26:11 UTC 2023 Jit Loon Lim <jit.loon.lim@intel.com> feat(intel): clock manager support for Agilex5 SoC FPGA
This patch is used to enable clock manager support
for Agilex5 SoC FPGA.
1. Added clock manager support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Standardized handoff handler.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic4c57a1955136ef7d22253c3ca52226e5620751b
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_clock_manager.c | 1b1a3eb1edff99b49bb40ad4172073d04a230938 Wed May 17 04:26:11 UTC 2023 Jit Loon Lim <jit.loon.lim@intel.com> feat(intel): clock manager support for Agilex5 SoC FPGA
This patch is used to enable clock manager support
for Agilex5 SoC FPGA.
1. Added clock manager support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Standardized handoff handler.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic4c57a1955136ef7d22253c3ca52226e5620751b
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