Searched hist:"18901324 e00a073b06dc413d6b7a87f1c0b2f8d1" (Results 1 – 5 of 5) sorted by relevance
| /optee_os/core/arch/arm/include/ |
| H A D | arm32.h | 18901324e00a073b06dc413d6b7a87f1c0b2f8d1 Wed Apr 05 10:30:07 UTC 2017 David Wang <david.wang@arm.com> Support ARM GICv3 mode
In ARM GICv3 mode, the interrupts are used as below for optee_os.
* FIQ - Foreign interrupts not handled by optee_os. This includes
the non-secure interrupts that should be handled by the REE and the
secure interrupts assigned to the monitor (aarch32 Monitor mode or
aarch64 EL3).
* IRQ - Native interrupts for optee_os.
And optee_os should use the system register interface to access the GICC
registers in GICv3 mode.
A new build flag `CFG_ARM_GICV3=y` should be set to support GICv3 mode.
Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | arm64.h | 18901324e00a073b06dc413d6b7a87f1c0b2f8d1 Wed Apr 05 10:30:07 UTC 2017 David Wang <david.wang@arm.com> Support ARM GICv3 mode
In ARM GICv3 mode, the interrupts are used as below for optee_os.
* FIQ - Foreign interrupts not handled by optee_os. This includes
the non-secure interrupts that should be handled by the REE and the
secure interrupts assigned to the monitor (aarch32 Monitor mode or
aarch64 EL3).
* IRQ - Native interrupts for optee_os.
And optee_os should use the system register interface to access the GICC
registers in GICv3 mode.
A new build flag `CFG_ARM_GICV3=y` should be set to support GICv3 mode.
Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/drivers/ |
| H A D | gic.c | 18901324e00a073b06dc413d6b7a87f1c0b2f8d1 Wed Apr 05 10:30:07 UTC 2017 David Wang <david.wang@arm.com> Support ARM GICv3 mode
In ARM GICv3 mode, the interrupts are used as below for optee_os.
* FIQ - Foreign interrupts not handled by optee_os. This includes
the non-secure interrupts that should be handled by the REE and the
secure interrupts assigned to the monitor (aarch32 Monitor mode or
aarch64 EL3).
* IRQ - Native interrupts for optee_os.
And optee_os should use the system register interface to access the GICC
registers in GICv3 mode.
A new build flag `CFG_ARM_GICV3=y` should be set to support GICv3 mode.
Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/arch/arm/kernel/ |
| H A D | thread_a32.S | 18901324e00a073b06dc413d6b7a87f1c0b2f8d1 Wed Apr 05 10:30:07 UTC 2017 David Wang <david.wang@arm.com> Support ARM GICv3 mode
In ARM GICv3 mode, the interrupts are used as below for optee_os.
* FIQ - Foreign interrupts not handled by optee_os. This includes
the non-secure interrupts that should be handled by the REE and the
secure interrupts assigned to the monitor (aarch32 Monitor mode or
aarch64 EL3).
* IRQ - Native interrupts for optee_os.
And optee_os should use the system register interface to access the GICC
registers in GICv3 mode.
A new build flag `CFG_ARM_GICV3=y` should be set to support GICv3 mode.
Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | thread_a64.S | 18901324e00a073b06dc413d6b7a87f1c0b2f8d1 Wed Apr 05 10:30:07 UTC 2017 David Wang <david.wang@arm.com> Support ARM GICv3 mode
In ARM GICv3 mode, the interrupts are used as below for optee_os.
* FIQ - Foreign interrupts not handled by optee_os. This includes
the non-secure interrupts that should be handled by the REE and the
secure interrupts assigned to the monitor (aarch32 Monitor mode or
aarch64 EL3).
* IRQ - Native interrupts for optee_os.
And optee_os should use the system register interface to access the GICC
registers in GICv3 mode.
A new build flag `CFG_ARM_GICV3=y` should be set to support GICv3 mode.
Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|