Searched hist:"14 c27f82930281709f2f947f2b9170dd37f42ac3" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/make_helpers/ |
| H A D | arch_features.mk | 14c27f82930281709f2f947f2b9170dd37f42ac3 Wed Apr 03 18:18:40 UTC 2024 Juan Pablo Conde <juanpablo.conde@arm.com> build(amu): restrict counters (RAZ)
The use of AMU counters at the highest implemented exception level
can expose information about them to lower exception levels, such as
specific behavior happening in the CPU (e.g.: MPMM gear shifting in
TC2). In order to prevent this, read accesses to AMU counters are
restricted by default, so they are RAZ (read-as-zero) from lower
exception levels from now on.
Change-Id: I660b0928bea3fe09436ad53b0bb43c3067523178
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
|
| /rk3399_ARM-atf/docs/getting_started/ |
| H A D | build-options.rst | 14c27f82930281709f2f947f2b9170dd37f42ac3 Wed Apr 03 18:18:40 UTC 2024 Juan Pablo Conde <juanpablo.conde@arm.com> build(amu): restrict counters (RAZ)
The use of AMU counters at the highest implemented exception level
can expose information about them to lower exception levels, such as
specific behavior happening in the CPU (e.g.: MPMM gear shifting in
TC2). In order to prevent this, read accesses to AMU counters are
restricted by default, so they are RAZ (read-as-zero) from lower
exception levels from now on.
Change-Id: I660b0928bea3fe09436ad53b0bb43c3067523178
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
|