1 /*
2 * Copyright (c) 2018-2023, Renesas Electronics Corporation. All rights reserved.
3 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <inttypes.h>
9 #include <stdint.h>
10 #include <string.h>
11
12 #include <libfdt.h>
13
14 #include <platform_def.h>
15
16 #include <arch_helpers.h>
17 #include <bl1/bl1.h>
18 #include <common/bl_common.h>
19 #include <common/debug.h>
20 #include <common/desc_image_load.h>
21 #include <common/image_decompress.h>
22 #include <drivers/console.h>
23 #include <drivers/io/io_driver.h>
24 #include <drivers/io/io_storage.h>
25 #include <lib/mmio.h>
26 #include <lib/xlat_tables/xlat_tables_defs.h>
27 #include <plat/common/platform.h>
28 #if RCAR_GEN3_BL33_GZIP == 1
29 #include <tf_gunzip.h>
30 #endif
31
32 #include "avs_driver.h"
33 #include "boot_init_dram.h"
34 #include "cpg_registers.h"
35 #include "board.h"
36 #include "emmc_def.h"
37 #include "emmc_hal.h"
38 #include "emmc_std.h"
39
40 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
41 #include "iic_dvfs.h"
42 #endif
43
44 #include "io_common.h"
45 #include "io_rcar.h"
46 #include "qos_init.h"
47 #include "rcar_def.h"
48 #include "rcar_private.h"
49 #include "rcar_version.h"
50 #include "rom_api.h"
51
52 /*
53 * Following symbols are only used during plat_arch_setup()
54 */
55 static const uint64_t BL2_RO_BASE = BL_CODE_BASE;
56 static const uint64_t BL2_RO_LIMIT = BL_CODE_END;
57
58 #if USE_COHERENT_MEM
59 static const uint64_t BL2_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
60 static const uint64_t BL2_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
61 #endif
62
63 extern void plat_rcar_gic_driver_init(void);
64 extern void plat_rcar_gic_init(void);
65 extern void bl2_enter_bl31(const struct entry_point_info *bl_ep_info);
66 extern void bl2_system_cpg_init(void);
67 extern void bl2_secure_setting(void);
68 extern void bl2_ram_security_setting_finish(void);
69 extern void bl2_cpg_init(void);
70 extern void rcar_io_emmc_setup(void);
71 extern void rcar_io_setup(void);
72 extern void rcar_swdt_release(void);
73 extern void rcar_swdt_init(void);
74 extern void rcar_rpc_init(void);
75 extern void rcar_pfc_init(void);
76 extern void rcar_dma_init(void);
77
78 static void bl2_init_generic_timer(void);
79
80 /* R-Car Gen3 product check */
81 #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
82 #define TARGET_PRODUCT PRR_PRODUCT_H3
83 #define TARGET_NAME "R-Car H3"
84 #elif RCAR_LSI == RCAR_M3
85 #define TARGET_PRODUCT PRR_PRODUCT_M3
86 #define TARGET_NAME "R-Car M3"
87 #elif RCAR_LSI == RCAR_M3N
88 #define TARGET_PRODUCT PRR_PRODUCT_M3N
89 #define TARGET_NAME "R-Car M3N"
90 #elif RCAR_LSI == RCAR_V3M
91 #define TARGET_PRODUCT PRR_PRODUCT_V3M
92 #define TARGET_NAME "R-Car V3M"
93 #elif RCAR_LSI == RCAR_E3
94 #define TARGET_PRODUCT PRR_PRODUCT_E3
95 #define TARGET_NAME "R-Car E3"
96 #elif RCAR_LSI == RCAR_D3
97 #define TARGET_PRODUCT PRR_PRODUCT_D3
98 #define TARGET_NAME "R-Car D3"
99 #elif RCAR_LSI == RCAR_AUTO
100 #define TARGET_NAME "R-Car H3/M3/M3N/V3M"
101 #endif
102
103 #if (RCAR_LSI == RCAR_E3)
104 #define GPIO_INDT (GPIO_INDT6)
105 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<13U)
106 #else
107 #define GPIO_INDT (GPIO_INDT1)
108 #define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U<<8U)
109 #endif
110
111 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
112 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
113 assert_bl31_params_do_not_fit_in_shared_memory);
114
115 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
116
117 /* FDT with DRAM configuration */
118 uint64_t fdt_blob[PAGE_SIZE_4KB / sizeof(uint64_t)];
119 static void *fdt = (void *)fdt_blob;
120
unsigned_num_print(unsigned long long int unum,unsigned int radix,char * string)121 static void unsigned_num_print(unsigned long long int unum, unsigned int radix,
122 char *string)
123 {
124 /* Just need enough space to store 64 bit decimal integer */
125 char num_buf[20];
126 int i = 0;
127 unsigned int rem;
128
129 do {
130 rem = unum % radix;
131 if (rem < 0xa)
132 num_buf[i] = '0' + rem;
133 else
134 num_buf[i] = 'a' + (rem - 0xa);
135 i++;
136 unum /= radix;
137 } while (unum > 0U);
138
139 while (--i >= 0)
140 *string++ = num_buf[i];
141 *string = 0;
142 }
143
144 #if (RCAR_LOSSY_ENABLE == 1)
145 typedef struct bl2_lossy_info {
146 uint32_t magic;
147 uint32_t a0;
148 uint32_t b0;
149 } bl2_lossy_info_t;
150
bl2_lossy_gen_fdt(uint32_t no,uint64_t start_addr,uint64_t end_addr,uint32_t format,uint32_t enable,int fcnlnode)151 static void bl2_lossy_gen_fdt(uint32_t no, uint64_t start_addr,
152 uint64_t end_addr, uint32_t format,
153 uint32_t enable, int fcnlnode)
154 {
155 const uint64_t fcnlsize = cpu_to_fdt64(end_addr - start_addr);
156 char nodename[40] = { 0 };
157 int ret, node;
158
159 /* Ignore undefined addresses */
160 if (start_addr == 0 && end_addr == 0)
161 return;
162
163 snprintf(nodename, sizeof(nodename), "lossy-decompression@");
164 unsigned_num_print(start_addr, 16, nodename + strlen(nodename));
165
166 node = ret = fdt_add_subnode(fdt, fcnlnode, nodename);
167 if (ret < 0) {
168 NOTICE("BL2: Cannot create FCNL node (ret=%i)\n", ret);
169 panic();
170 }
171
172 ret = fdt_setprop_string(fdt, node, "compatible",
173 "renesas,lossy-decompression");
174 if (ret < 0) {
175 NOTICE("BL2: Cannot add FCNL compat string (ret=%i)\n", ret);
176 panic();
177 }
178
179 ret = fdt_appendprop_string(fdt, node, "compatible",
180 "shared-dma-pool");
181 if (ret < 0) {
182 NOTICE("BL2: Cannot append FCNL compat string (ret=%i)\n", ret);
183 panic();
184 }
185
186 ret = fdt_setprop_u64(fdt, node, "reg", start_addr);
187 if (ret < 0) {
188 NOTICE("BL2: Cannot add FCNL reg prop (ret=%i)\n", ret);
189 panic();
190 }
191
192 ret = fdt_appendprop(fdt, node, "reg", &fcnlsize, sizeof(fcnlsize));
193 if (ret < 0) {
194 NOTICE("BL2: Cannot append FCNL reg size prop (ret=%i)\n", ret);
195 panic();
196 }
197
198 ret = fdt_setprop(fdt, node, "no-map", NULL, 0);
199 if (ret < 0) {
200 NOTICE("BL2: Cannot add FCNL no-map prop (ret=%i)\n", ret);
201 panic();
202 }
203
204 ret = fdt_setprop_u32(fdt, node, "renesas,formats", format);
205 if (ret < 0) {
206 NOTICE("BL2: Cannot add FCNL formats prop (ret=%i)\n", ret);
207 panic();
208 }
209 }
210
bl2_lossy_setting(uint32_t no,uint64_t start_addr,uint64_t end_addr,uint32_t format,uint32_t enable,int fcnlnode)211 static void bl2_lossy_setting(uint32_t no, uint64_t start_addr,
212 uint64_t end_addr, uint32_t format,
213 uint32_t enable, int fcnlnode)
214 {
215 bl2_lossy_info_t info;
216 uint32_t reg;
217
218 bl2_lossy_gen_fdt(no, start_addr, end_addr, format, enable, fcnlnode);
219
220 reg = format | (start_addr >> 20);
221 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg);
222 mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, end_addr >> 20);
223 mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg | enable);
224
225 info.magic = 0x12345678U;
226 info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no);
227 info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no);
228
229 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no, info.magic);
230 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x4, info.a0);
231 mmio_write_32(LOSSY_PARAMS_BASE + sizeof(info) * no + 0x8, info.b0);
232
233 NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no,
234 mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no),
235 mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no));
236 }
237
bl2_create_reserved_memory(void)238 static int bl2_create_reserved_memory(void)
239 {
240 int ret;
241
242 int fcnlnode = fdt_add_subnode(fdt, 0, "reserved-memory");
243 if (fcnlnode < 0) {
244 NOTICE("BL2: Cannot create reserved mem node (ret=%i)\n",
245 fcnlnode);
246 panic();
247 }
248
249 ret = fdt_setprop(fdt, fcnlnode, "ranges", NULL, 0);
250 if (ret < 0) {
251 NOTICE("BL2: Cannot add FCNL ranges prop (ret=%i)\n", ret);
252 panic();
253 }
254
255 ret = fdt_setprop_u32(fdt, fcnlnode, "#address-cells", 2);
256 if (ret < 0) {
257 NOTICE("BL2: Cannot add FCNL #address-cells prop (ret=%i)\n", ret);
258 panic();
259 }
260
261 ret = fdt_setprop_u32(fdt, fcnlnode, "#size-cells", 2);
262 if (ret < 0) {
263 NOTICE("BL2: Cannot add FCNL #size-cells prop (ret=%i)\n", ret);
264 panic();
265 }
266
267 return fcnlnode;
268 }
269
bl2_create_fcnl_reserved_memory(void)270 static void bl2_create_fcnl_reserved_memory(void)
271 {
272 int fcnlnode;
273
274 NOTICE("BL2: Lossy Decomp areas\n");
275
276 fcnlnode = bl2_create_reserved_memory();
277
278 bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0,
279 LOSSY_FMT0, LOSSY_ENA_DIS0, fcnlnode);
280 bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1,
281 LOSSY_FMT1, LOSSY_ENA_DIS1, fcnlnode);
282 bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2,
283 LOSSY_FMT2, LOSSY_ENA_DIS2, fcnlnode);
284 }
285 #else
bl2_create_fcnl_reserved_memory(void)286 static void bl2_create_fcnl_reserved_memory(void) {}
287 #endif
288
bl2_plat_flush_bl31_params(void)289 void bl2_plat_flush_bl31_params(void)
290 {
291 uint32_t product_cut, product, cut;
292 uint32_t boot_dev, boot_cpu;
293 uint32_t lcs, reg, val;
294
295 reg = mmio_read_32(RCAR_MODEMR);
296 boot_dev = reg & MODEMR_BOOT_DEV_MASK;
297
298 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
299 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
300 emmc_terminate();
301
302 if ((reg & MODEMR_BOOT_CPU_MASK) != MODEMR_BOOT_CPU_CR7)
303 bl2_secure_setting();
304
305 reg = mmio_read_32(RCAR_PRR);
306 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
307 product = reg & PRR_PRODUCT_MASK;
308 cut = reg & PRR_CUT_MASK;
309
310 if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut)
311 goto tlb;
312
313 if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut)
314 goto tlb;
315
316 /* Disable MFIS write protection */
317 mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1);
318
319 tlb:
320 reg = mmio_read_32(RCAR_MODEMR);
321 boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
322 if (boot_cpu != MODEMR_BOOT_CPU_CA57 &&
323 boot_cpu != MODEMR_BOOT_CPU_CA53)
324 goto mmu;
325
326 if (product_cut == PRR_PRODUCT_H3_CUT20) {
327 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
328 mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
329 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
330 mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
331 mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
332 mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
333 } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
334 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) {
335 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
336 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
337 } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) ||
338 (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) {
339 mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
340 mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
341 mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
342 }
343
344 if (product_cut == (PRR_PRODUCT_H3_CUT20) ||
345 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
346 product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) ||
347 product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) {
348 mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
349 mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
350 mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
351
352 mmio_write_32(IPMMUDS0_IMSCTLR, IMSCTLR_DISCACHE);
353 mmio_write_32(IPMMUDS1_IMSCTLR, IMSCTLR_DISCACHE);
354 }
355
356 mmu:
357 mmio_write_32(IPMMUMM_IMSCTLR, IPMMUMM_IMSCTLR_ENABLE);
358 mmio_write_32(IPMMUMM_IMAUXCTLR, IPMMUMM_IMAUXCTLR_NMERGE40_BIT);
359
360 val = rcar_rom_get_lcs(&lcs);
361 if (val) {
362 ERROR("BL2: Failed to get the LCS. (%d)\n", val);
363 panic();
364 }
365
366 if (lcs == LCS_SE)
367 mmio_clrbits_32(P_ARMREG_SEC_CTRL, P_ARMREG_SEC_CTRL_PROT);
368
369 rcar_swdt_release();
370 bl2_system_cpg_init();
371
372 /* Disable data cache (clean and invalidate) */
373 disable_mmu_el3();
374 #if RCAR_BL2_DCACHE == 1
375 dcsw_op_all(DCCISW);
376 #endif
377 tlbialle3();
378 disable_mmu_icache_el3();
379 plat_invalidate_icache();
380 dsbsy();
381 isb();
382 }
383
is_ddr_backup_mode(void)384 static uint32_t is_ddr_backup_mode(void)
385 {
386 #if RCAR_SYSTEM_SUSPEND
387 static uint32_t reason = RCAR_COLD_BOOT;
388 static uint32_t once;
389
390 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
391 uint8_t data;
392 #endif
393 if (once)
394 return reason;
395
396 once = 1;
397 if ((mmio_read_32(GPIO_INDT) & GPIO_BKUP_TRG_SHIFT) == 0)
398 return reason;
399
400 #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
401 if (rcar_iic_dvfs_receive(PMIC, REG_KEEP10, &data)) {
402 ERROR("BL2: REG Keep10 READ ERROR.\n");
403 panic();
404 }
405
406 if (KEEP10_MAGIC != data)
407 reason = RCAR_WARM_BOOT;
408 #else
409 reason = RCAR_WARM_BOOT;
410 #endif
411 return reason;
412 #else
413 return RCAR_COLD_BOOT;
414 #endif
415 }
416
417 #if RCAR_GEN3_BL33_GZIP == 1
bl2_plat_preload_setup(void)418 void bl2_plat_preload_setup(void)
419 {
420 image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip);
421 }
422 #endif
423
check_secure_load_area(uintptr_t base,uint32_t size,uintptr_t dest,uint32_t len)424 static uint64_t check_secure_load_area(uintptr_t base, uint32_t size,
425 uintptr_t dest, uint32_t len)
426 {
427 uintptr_t free_end, requested_end;
428
429 /*
430 * Handle corner cases first.
431 *
432 * The order of the 2 tests is important, because if there's no space
433 * left (i.e. free_size == 0) but we don't ask for any memory
434 * (i.e. size == 0) then we should report that the memory is free.
435 */
436 if (len == 0U) {
437 WARN("BL2: load data size is zero\n");
438 return 0; /* A zero-byte region is always free */
439 }
440 if (size == 0U) {
441 goto err;
442 }
443
444 /*
445 * Check that the end addresses don't overflow.
446 * If they do, consider that this memory region is not free, as this
447 * is an invalid scenario.
448 */
449 if (check_uptr_overflow(base, size - 1U)) {
450 goto err;
451 }
452 free_end = base + (size - 1U);
453
454 if (check_uptr_overflow(dest, len - 1U)) {
455 goto err;
456 }
457 requested_end = dest + (len - 1U);
458
459 /*
460 * Finally, check that the requested memory region lies within the free
461 * region.
462 */
463 if ((dest < base) || (requested_end > free_end)) {
464 goto err;
465 }
466
467 return 0;
468
469 err:
470 ERROR("BL2: load data is outside the loadable area.\n");
471 ERROR("BL2: dst=0x%lx, len=%d(0x%x)\n", dest, len, len);
472 return 1;
473 }
474
rcar_get_dest_addr_from_cert(uint32_t certid,uintptr_t * dest,uint32_t * len)475 static uint64_t rcar_get_dest_addr_from_cert(uint32_t certid, uintptr_t *dest,
476 uint32_t *len)
477 {
478 uint32_t cert;
479 int ret;
480
481 ret = rcar_get_certificate(certid, &cert);
482 if (ret) {
483 ERROR("%s : cert file load error", __func__);
484 return 1;
485 }
486
487 rcar_read_certificate((uint64_t) cert, len, dest);
488
489 return 0;
490 }
491
bl2_plat_handle_pre_image_load(unsigned int image_id)492 int bl2_plat_handle_pre_image_load(unsigned int image_id)
493 {
494 u_register_t *boot_kind = (void *) BOOT_KIND_BASE;
495 bl_mem_params_node_t *bl_mem_params;
496 uintptr_t dev_handle;
497 uintptr_t image_spec;
498 uintptr_t dest;
499 uint32_t len;
500 uint64_t ui64_ret;
501 int iret;
502
503 bl_mem_params = get_bl_mem_params_node(image_id);
504 if (bl_mem_params == NULL) {
505 ERROR("BL2: Failed to get loading parameter.\n");
506 return 1;
507 }
508
509 switch (image_id) {
510 case BL31_IMAGE_ID:
511 if (is_ddr_backup_mode() == RCAR_COLD_BOOT) {
512 iret = plat_get_image_source(image_id, &dev_handle,
513 &image_spec);
514 if (iret != 0) {
515 return 1;
516 }
517
518 ui64_ret = rcar_get_dest_addr_from_cert(
519 SOC_FW_CONTENT_CERT_ID, &dest, &len);
520 if (ui64_ret != 0U) {
521 return 1;
522 }
523
524 ui64_ret = check_secure_load_area(
525 BL31_BASE, BL31_LIMIT - BL31_BASE,
526 dest, len);
527 if (ui64_ret != 0U) {
528 return 1;
529 }
530
531 *boot_kind = RCAR_COLD_BOOT;
532 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
533
534 bl_mem_params->image_info.image_base = dest;
535 bl_mem_params->image_info.image_size = len;
536 } else {
537 *boot_kind = RCAR_WARM_BOOT;
538 flush_dcache_range(BOOT_KIND_BASE, sizeof(*boot_kind));
539
540 console_flush();
541 bl2_plat_flush_bl31_params();
542
543 /* will not return */
544 bl2_enter_bl31(&bl_mem_params->ep_info);
545 }
546
547 return 0;
548 #ifndef SPD_NONE
549 case BL32_IMAGE_ID:
550 ui64_ret = rcar_get_dest_addr_from_cert(
551 TRUSTED_OS_FW_CONTENT_CERT_ID, &dest, &len);
552 if (ui64_ret != 0U) {
553 return 1;
554 }
555
556 ui64_ret = check_secure_load_area(
557 BL32_BASE, BL32_LIMIT - BL32_BASE, dest, len);
558 if (ui64_ret != 0U) {
559 return 1;
560 }
561
562 bl_mem_params->image_info.image_base = dest;
563 bl_mem_params->image_info.image_size = len;
564
565 return 0;
566 #endif
567 case BL33_IMAGE_ID:
568 /* case of image_id == BL33_IMAGE_ID */
569 ui64_ret = rcar_get_dest_addr_from_cert(
570 NON_TRUSTED_FW_CONTENT_CERT_ID,
571 &dest, &len);
572
573 if (ui64_ret != 0U) {
574 return 1;
575 }
576
577 bl_mem_params->image_info.image_base = dest;
578 bl_mem_params->image_info.image_size = len;
579
580 #if RCAR_GEN3_BL33_GZIP == 1
581 image_decompress_prepare(&bl_mem_params->image_info);
582 #endif
583
584 return 0;
585 default:
586 return 1;
587 }
588
589 return 0;
590 }
591
bl2_plat_handle_post_image_load(unsigned int image_id)592 int bl2_plat_handle_post_image_load(unsigned int image_id)
593 {
594 static bl2_to_bl31_params_mem_t *params;
595 bl_mem_params_node_t *bl_mem_params;
596
597 if (!params) {
598 params = (bl2_to_bl31_params_mem_t *) PARAMS_BASE;
599 memset((void *)PARAMS_BASE, 0, sizeof(*params));
600 }
601
602 bl_mem_params = get_bl_mem_params_node(image_id);
603 if (!bl_mem_params) {
604 ERROR("BL2: Failed to get loading parameter.\n");
605 return 1;
606 }
607
608 switch (image_id) {
609 case BL31_IMAGE_ID:
610 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
611 return 0;
612 case BL32_IMAGE_ID:
613 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
614 memcpy(¶ms->bl32_ep_info, &bl_mem_params->ep_info,
615 sizeof(entry_point_info_t));
616 return 0;
617 case BL33_IMAGE_ID:
618 #if RCAR_GEN3_BL33_GZIP == 1
619 int ret;
620 if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) {
621 /* decompress gzip-compressed image */
622 ret = image_decompress(&bl_mem_params->image_info);
623 if (ret != 0) {
624 return ret;
625 }
626 } else {
627 /* plain image, copy it in place */
628 memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE,
629 bl_mem_params->image_info.image_size);
630 }
631 #endif
632 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
633 memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info,
634 sizeof(entry_point_info_t));
635 return 0;
636 default:
637 return 1;
638 }
639
640 return 0;
641 }
642
bl2_plat_sec_mem_layout(void)643 struct meminfo *bl2_plat_sec_mem_layout(void)
644 {
645 return &bl2_tzram_layout;
646 }
647
bl2_populate_compatible_string(void * dt)648 static void bl2_populate_compatible_string(void *dt)
649 {
650 uint32_t board_type;
651 uint32_t board_rev;
652 uint32_t reg;
653 int ret;
654
655 fdt_setprop_u32(dt, 0, "#address-cells", 2);
656 fdt_setprop_u32(dt, 0, "#size-cells", 2);
657
658 /* Populate compatible string */
659 rcar_get_board_type(&board_type, &board_rev);
660 switch (board_type) {
661 case BOARD_SALVATOR_X:
662 ret = fdt_setprop_string(dt, 0, "compatible",
663 "renesas,salvator-x");
664 break;
665 case BOARD_SALVATOR_XS:
666 ret = fdt_setprop_string(dt, 0, "compatible",
667 "renesas,salvator-xs");
668 break;
669 case BOARD_STARTER_KIT:
670 ret = fdt_setprop_string(dt, 0, "compatible",
671 "renesas,m3ulcb");
672 break;
673 case BOARD_STARTER_KIT_PRE:
674 ret = fdt_setprop_string(dt, 0, "compatible",
675 "renesas,h3ulcb");
676 break;
677 case BOARD_EAGLE:
678 ret = fdt_setprop_string(dt, 0, "compatible",
679 "renesas,eagle");
680 break;
681 case BOARD_EBISU:
682 case BOARD_EBISU_4D:
683 ret = fdt_setprop_string(dt, 0, "compatible",
684 "renesas,ebisu");
685 break;
686 case BOARD_DRAAK:
687 ret = fdt_setprop_string(dt, 0, "compatible",
688 "renesas,draak");
689 break;
690 default:
691 NOTICE("BL2: Cannot set compatible string, board unsupported\n");
692 panic();
693 }
694
695 if (ret < 0) {
696 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
697 panic();
698 }
699
700 reg = mmio_read_32(RCAR_PRR);
701 switch (reg & PRR_PRODUCT_MASK) {
702 case PRR_PRODUCT_H3:
703 ret = fdt_appendprop_string(dt, 0, "compatible",
704 "renesas,r8a7795");
705 break;
706 case PRR_PRODUCT_M3:
707 ret = fdt_appendprop_string(dt, 0, "compatible",
708 "renesas,r8a7796");
709 break;
710 case PRR_PRODUCT_M3N:
711 ret = fdt_appendprop_string(dt, 0, "compatible",
712 "renesas,r8a77965");
713 break;
714 case PRR_PRODUCT_V3M:
715 ret = fdt_appendprop_string(dt, 0, "compatible",
716 "renesas,r8a77970");
717 break;
718 case PRR_PRODUCT_E3:
719 ret = fdt_appendprop_string(dt, 0, "compatible",
720 "renesas,r8a77990");
721 break;
722 case PRR_PRODUCT_D3:
723 ret = fdt_appendprop_string(dt, 0, "compatible",
724 "renesas,r8a77995");
725 break;
726 default:
727 NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
728 panic();
729 }
730
731 if (ret < 0) {
732 NOTICE("BL2: Cannot set compatible string (ret=%i)\n", ret);
733 panic();
734 }
735 }
736
bl2_add_rpc_node(void)737 static void bl2_add_rpc_node(void)
738 {
739 #if (RCAR_RPC_HYPERFLASH_LOCKED == 0)
740 int ret, node;
741
742 node = ret = fdt_add_subnode(fdt, 0, "soc");
743 if (ret < 0) {
744 goto err;
745 }
746
747 node = ret = fdt_add_subnode(fdt, node, "spi@ee200000");
748 if (ret < 0) {
749 goto err;
750 }
751
752 ret = fdt_setprop_string(fdt, node, "status", "okay");
753 if (ret < 0) {
754 goto err;
755 }
756
757 return;
758 err:
759 NOTICE("BL2: Cannot add RPC node to FDT (ret=%i)\n", ret);
760 panic();
761 #endif
762 }
763
bl2_add_kaslr_seed(void)764 static void bl2_add_kaslr_seed(void)
765 {
766 uint32_t cnt, isr, prr;
767 uint64_t seed;
768 int ret, node;
769
770 /* SCEG is only available on H3/M3-W/M3-N */
771 prr = mmio_read_32(RCAR_PRR);
772 switch (prr & PRR_PRODUCT_MASK) {
773 case PRR_PRODUCT_H3:
774 case PRR_PRODUCT_M3:
775 case PRR_PRODUCT_M3N:
776 break;
777 default:
778 return;
779 }
780
781 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_SW_RESET_REG_ADDR,
782 CC63_TRNG_SW_RESET_REG_SET);
783
784 do {
785 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_CLK_ENABLE_REG_ADDR,
786 CC63_TRNG_CLK_ENABLE_REG_SET);
787 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_SAMPLE_CNT1_REG_ADDR,
788 CC63_TRNG_SAMPLE_CNT1_REG_SAMPLE_COUNT);
789 cnt = mmio_read_32(RCAR_CC63_BASE + CC63_TRNG_SAMPLE_CNT1_REG_ADDR);
790 } while (cnt != CC63_TRNG_SAMPLE_CNT1_REG_SAMPLE_COUNT);
791
792 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_CONFIG_REG_ADDR,
793 CC63_TRNG_CONFIG_REG_ROSC_MAX_LENGTH);
794 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_DEBUG_CONTROL_REG_ADDR,
795 CC63_TRNG_DEBUG_CONTROL_REG_80090B);
796 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_SOURCE_ENABLE_REG_ADDR,
797 CC63_TRNG_SOURCE_ENABLE_REG_SET);
798
799 do {
800 isr = mmio_read_32(RCAR_CC63_BASE + CC63_TRNG_ISR_REG_ADDR);
801 if ((isr & CC63_TRNG_ISR_REG_AUTOCORR_ERR) != 0U) {
802 panic();
803 }
804 } while ((isr & CC63_TRNG_ISR_REG_EHR_VALID) == 0U);
805
806 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_ICR_REG_ADDR, UINT32_MAX);
807 seed = mmio_read_64(RCAR_CC63_BASE + CC63_TRNG_EHR_DATA_ADDR_0_REG_ADDR);
808 mmio_write_32(RCAR_CC63_BASE + CC63_TRNG_SOURCE_ENABLE_REG_ADDR,
809 CC63_TRNG_SOURCE_ENABLE_REG_CLR);
810
811 node = ret = fdt_add_subnode(fdt, 0, "chosen");
812 if (ret < 0) {
813 goto err;
814 }
815
816 ret = fdt_setprop_u64(fdt, node, "kaslr-seed", seed);
817 if (ret < 0) {
818 goto err;
819 }
820
821 return;
822 err:
823 NOTICE("BL2: Cannot add KASLR seed to FDT (ret=%i)\n", ret);
824 panic();
825 }
826
bl2_add_dram_entry(uint64_t start,uint64_t size)827 static void bl2_add_dram_entry(uint64_t start, uint64_t size)
828 {
829 char nodename[32] = { 0 };
830 uint64_t fdtsize;
831 int ret, node;
832
833 fdtsize = cpu_to_fdt64(size);
834
835 snprintf(nodename, sizeof(nodename), "memory@");
836 unsigned_num_print(start, 16, nodename + strlen(nodename));
837 node = ret = fdt_add_subnode(fdt, 0, nodename);
838 if (ret < 0) {
839 goto err;
840 }
841
842 ret = fdt_setprop_string(fdt, node, "device_type", "memory");
843 if (ret < 0) {
844 goto err;
845 }
846
847 ret = fdt_setprop_u64(fdt, node, "reg", start);
848 if (ret < 0) {
849 goto err;
850 }
851
852 ret = fdt_appendprop(fdt, node, "reg", &fdtsize,
853 sizeof(fdtsize));
854 if (ret < 0) {
855 goto err;
856 }
857
858 return;
859 err:
860 NOTICE("BL2: Cannot add memory node [%" PRIx64 " - %" PRIx64 "] to FDT (ret=%i)\n",
861 start, start + size - 1, ret);
862 panic();
863 }
864
bl2_advertise_dram_entries(uint64_t dram_config[8])865 static void bl2_advertise_dram_entries(uint64_t dram_config[8])
866 {
867 uint64_t start, size, size32;
868 int chan;
869
870 for (chan = 0; chan < 4; chan++) {
871 start = dram_config[2 * chan];
872 size = dram_config[2 * chan + 1];
873 if (!size)
874 continue;
875
876 NOTICE("BL2: CH%d: %" PRIx64 " - %" PRIx64 ", %" PRId64 " %siB\n",
877 chan, start, start + size - 1,
878 (size >> 30) ? : size >> 20,
879 (size >> 30) ? "G" : "M");
880 }
881
882 /*
883 * We add the DT nodes in reverse order here. The fdt_add_subnode()
884 * adds the DT node before the first existing DT node, so we have
885 * to add them in reverse order to get nodes sorted by address in
886 * the resulting DT.
887 */
888 for (chan = 3; chan >= 0; chan--) {
889 start = dram_config[2 * chan];
890 size = dram_config[2 * chan + 1];
891 if (!size)
892 continue;
893
894 /*
895 * Channel 0 is mapped in 32bit space and the first
896 * 128 MiB are reserved and the maximum size is 2GiB.
897 */
898 if (chan == 0) {
899 /* Limit the 32bit entry to 2 GiB - 128 MiB */
900 size32 = size - 0x8000000U;
901 if (size32 >= 0x78000000U) {
902 size32 = 0x78000000U;
903 }
904
905 /* Emit 32bit entry, up to 2 GiB - 128 MiB long. */
906 bl2_add_dram_entry(0x48000000, size32);
907
908 /*
909 * If channel 0 is less than 2 GiB long, the
910 * entire memory fits into the 32bit space entry,
911 * so move on to the next channel.
912 */
913 if (size <= 0x80000000U) {
914 continue;
915 }
916
917 /*
918 * If channel 0 is more than 2 GiB long, emit
919 * another entry which covers the rest of the
920 * memory in channel 0, in the 64bit space.
921 *
922 * Start of this new entry is at 2 GiB offset
923 * from the beginning of the 64bit channel 0
924 * address, size is 2 GiB shorter than total
925 * size of the channel.
926 */
927 start += 0x80000000U;
928 size -= 0x80000000U;
929 }
930
931 bl2_add_dram_entry(start, size);
932 }
933 }
934
bl2_advertise_dram_size(uint32_t product)935 static void bl2_advertise_dram_size(uint32_t product)
936 {
937 uint64_t dram_config[8] = {
938 [0] = 0x400000000ULL,
939 [2] = 0x500000000ULL,
940 [4] = 0x600000000ULL,
941 [6] = 0x700000000ULL,
942 };
943 uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
944
945 switch (product) {
946 case PRR_PRODUCT_H3:
947 #if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
948 /* 4GB(1GBx4) */
949 dram_config[1] = 0x40000000ULL;
950 dram_config[3] = 0x40000000ULL;
951 dram_config[5] = 0x40000000ULL;
952 dram_config[7] = 0x40000000ULL;
953 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \
954 (RCAR_DRAM_CHANNEL == 5) && \
955 (RCAR_DRAM_SPLIT == 2)
956 /* 4GB(2GBx2 2ch split) */
957 dram_config[1] = 0x80000000ULL;
958 dram_config[3] = 0x80000000ULL;
959 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15)
960 /* 8GB(2GBx4: default) */
961 dram_config[1] = 0x80000000ULL;
962 dram_config[3] = 0x80000000ULL;
963 dram_config[5] = 0x80000000ULL;
964 dram_config[7] = 0x80000000ULL;
965 #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
966 break;
967
968 case PRR_PRODUCT_M3:
969 if (cut < PRR_PRODUCT_30) {
970 #if (RCAR_GEN3_ULCB == 1)
971 /* 2GB(1GBx2 2ch split) */
972 dram_config[1] = 0x40000000ULL;
973 dram_config[5] = 0x40000000ULL;
974 #else
975 /* 4GB(2GBx2 2ch split) */
976 dram_config[1] = 0x80000000ULL;
977 dram_config[5] = 0x80000000ULL;
978 #endif
979 } else {
980 /* 8GB(2GBx4 2ch split) */
981 dram_config[1] = 0x100000000ULL;
982 dram_config[5] = 0x100000000ULL;
983 }
984 break;
985
986 case PRR_PRODUCT_M3N:
987 #if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
988 /* 4GB(4GBx1) */
989 dram_config[1] = 0x100000000ULL;
990 #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1)
991 /* 2GB(1GBx2) */
992 dram_config[1] = 0x80000000ULL;
993 #endif
994 break;
995
996 case PRR_PRODUCT_V3M:
997 /* 1GB(512MBx2) */
998 dram_config[1] = 0x40000000ULL;
999 break;
1000
1001 case PRR_PRODUCT_E3:
1002 #if (RCAR_DRAM_DDR3L_MEMCONF == 0)
1003 /* 1GB(512MBx2) */
1004 dram_config[1] = 0x40000000ULL;
1005 #elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
1006 /* 2GB(512MBx4) */
1007 dram_config[1] = 0x80000000ULL;
1008 #elif (RCAR_DRAM_DDR3L_MEMCONF == 2)
1009 /* 4GB(1GBx4) */
1010 dram_config[1] = 0x100000000ULL;
1011 #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
1012 break;
1013
1014 case PRR_PRODUCT_D3:
1015 /* 512MB */
1016 dram_config[1] = 0x20000000ULL;
1017 break;
1018 }
1019
1020 bl2_advertise_dram_entries(dram_config);
1021 }
1022
bl2_early_platform_setup2(u_register_t arg1,u_register_t arg2,u_register_t arg3,u_register_t arg4)1023 void bl2_early_platform_setup2(u_register_t arg1, u_register_t arg2,
1024 u_register_t arg3, u_register_t arg4)
1025 {
1026 uint32_t reg, midr, lcs, boot_dev, boot_cpu, sscg, type, rev;
1027 uint32_t product, product_cut, major, minor;
1028 int32_t ret;
1029 const char *str;
1030 const char *unknown = "unknown";
1031 const char *cpu_ca57 = "CA57";
1032 const char *cpu_ca53 = "CA53";
1033 const char *product_m3n = "M3N";
1034 const char *product_h3 = "H3";
1035 const char *product_m3 = "M3";
1036 const char *product_e3 = "E3";
1037 const char *product_d3 = "D3";
1038 const char *product_v3m = "V3M";
1039 const char *lcs_secure = "SE";
1040 const char *lcs_cm = "CM";
1041 const char *lcs_dm = "DM";
1042 const char *lcs_sd = "SD";
1043 const char *lcs_fa = "FA";
1044 const char *sscg_off = "PLL1 nonSSCG Clock select";
1045 const char *sscg_on = "PLL1 SSCG Clock select";
1046 const char *boot_hyper80 = "HyperFlash(80MHz)";
1047 const char *boot_qspi40 = "QSPI Flash(40MHz)";
1048 const char *boot_qspi80 = "QSPI Flash(80MHz)";
1049 const char *boot_emmc25x1 = "eMMC(25MHz x1)";
1050 const char *boot_emmc50x8 = "eMMC(50MHz x8)";
1051 #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
1052 const char *boot_hyper160 = "HyperFlash(150MHz)";
1053 #else
1054 const char *boot_hyper160 = "HyperFlash(160MHz)";
1055 #endif
1056
1057 bl2_init_generic_timer();
1058
1059 reg = mmio_read_32(RCAR_MODEMR);
1060 boot_dev = reg & MODEMR_BOOT_DEV_MASK;
1061 boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
1062
1063 bl2_cpg_init();
1064
1065 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
1066 boot_cpu == MODEMR_BOOT_CPU_CA53) {
1067 rcar_pfc_init();
1068 rcar_console_boot_init();
1069 }
1070
1071 plat_rcar_gic_driver_init();
1072 plat_rcar_gic_init();
1073 rcar_swdt_init();
1074
1075 /* FIQ interrupts are taken to EL3 */
1076 write_scr_el3(read_scr_el3() | SCR_FIQ_BIT);
1077
1078 write_daifclr(DAIF_FIQ_BIT);
1079
1080 reg = read_midr();
1081 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT);
1082 switch (midr) {
1083 case MIDR_CA57:
1084 str = cpu_ca57;
1085 break;
1086 case MIDR_CA53:
1087 str = cpu_ca53;
1088 break;
1089 default:
1090 str = unknown;
1091 break;
1092 }
1093
1094 NOTICE("BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n", str,
1095 version_of_renesas);
1096
1097 reg = mmio_read_32(RCAR_PRR);
1098 product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
1099 product = reg & PRR_PRODUCT_MASK;
1100
1101 switch (product) {
1102 case PRR_PRODUCT_H3:
1103 str = product_h3;
1104 break;
1105 case PRR_PRODUCT_M3:
1106 str = product_m3;
1107 break;
1108 case PRR_PRODUCT_M3N:
1109 str = product_m3n;
1110 break;
1111 case PRR_PRODUCT_V3M:
1112 str = product_v3m;
1113 break;
1114 case PRR_PRODUCT_E3:
1115 str = product_e3;
1116 break;
1117 case PRR_PRODUCT_D3:
1118 str = product_d3;
1119 break;
1120 default:
1121 str = unknown;
1122 break;
1123 }
1124
1125 if ((PRR_PRODUCT_M3 == product) &&
1126 (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) {
1127 if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
1128 /* M3 Ver.1.1 or Ver.1.2 */
1129 NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n",
1130 str);
1131 } else {
1132 NOTICE("BL2: PRR is R-Car %s Ver.1.%d\n",
1133 str,
1134 (reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET);
1135 }
1136 } else if (product == PRR_PRODUCT_D3) {
1137 if (RCAR_D3_CUT_VER10 == (reg & PRR_CUT_MASK)) {
1138 NOTICE("BL2: PRR is R-Car %s Ver.1.0\n", str);
1139 } else if (RCAR_D3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
1140 NOTICE("BL2: PRR is R-Car %s Ver.1.1\n", str);
1141 } else {
1142 NOTICE("BL2: PRR is R-Car %s Ver.X.X\n", str);
1143 }
1144 } else {
1145 major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
1146 major = major + RCAR_MAJOR_OFFSET;
1147 minor = reg & RCAR_MINOR_MASK;
1148 NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
1149 }
1150
1151 if (PRR_PRODUCT_E3 == product || PRR_PRODUCT_D3 == product) {
1152 reg = mmio_read_32(RCAR_MODEMR);
1153 sscg = reg & RCAR_SSCG_MASK;
1154 str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
1155 NOTICE("BL2: %s\n", str);
1156 }
1157
1158 rcar_get_board_type(&type, &rev);
1159
1160 switch (type) {
1161 case BOARD_SALVATOR_X:
1162 case BOARD_KRIEK:
1163 case BOARD_STARTER_KIT:
1164 case BOARD_SALVATOR_XS:
1165 case BOARD_EBISU:
1166 case BOARD_STARTER_KIT_PRE:
1167 case BOARD_EBISU_4D:
1168 case BOARD_DRAAK:
1169 case BOARD_EAGLE:
1170 break;
1171 default:
1172 type = BOARD_UNKNOWN;
1173 break;
1174 }
1175
1176 if (type == BOARD_UNKNOWN || rev == BOARD_REV_UNKNOWN)
1177 NOTICE("BL2: Board is %s Rev.---\n", GET_BOARD_NAME(type));
1178 else {
1179 NOTICE("BL2: Board is %s Rev.%d.%d\n",
1180 GET_BOARD_NAME(type),
1181 GET_BOARD_MAJOR(rev), GET_BOARD_MINOR(rev));
1182 }
1183
1184 #if RCAR_LSI != RCAR_AUTO
1185 if (product != TARGET_PRODUCT) {
1186 ERROR("BL2: IPL was been built for the %s.\n", TARGET_NAME);
1187 ERROR("BL2: Please write the correct IPL to flash memory.\n");
1188 panic();
1189 }
1190 #endif
1191 rcar_avs_init();
1192 rcar_avs_setting();
1193
1194 switch (boot_dev) {
1195 case MODEMR_BOOT_DEV_HYPERFLASH160:
1196 str = boot_hyper160;
1197 break;
1198 case MODEMR_BOOT_DEV_HYPERFLASH80:
1199 str = boot_hyper80;
1200 break;
1201 case MODEMR_BOOT_DEV_QSPI_FLASH40:
1202 str = boot_qspi40;
1203 break;
1204 case MODEMR_BOOT_DEV_QSPI_FLASH80:
1205 str = boot_qspi80;
1206 break;
1207 case MODEMR_BOOT_DEV_EMMC_25X1:
1208 #if RCAR_LSI == RCAR_D3
1209 ERROR("BL2: Failed to Initialize. eMMC is not supported.\n");
1210 panic();
1211 #endif
1212 str = boot_emmc25x1;
1213 break;
1214 case MODEMR_BOOT_DEV_EMMC_50X8:
1215 str = boot_emmc50x8;
1216 break;
1217 default:
1218 str = unknown;
1219 break;
1220 }
1221 NOTICE("BL2: Boot device is %s\n", str);
1222
1223 rcar_avs_setting();
1224 reg = rcar_rom_get_lcs(&lcs);
1225 if (reg) {
1226 str = unknown;
1227 goto lcm_state;
1228 }
1229
1230 switch (lcs) {
1231 case LCS_CM:
1232 str = lcs_cm;
1233 break;
1234 case LCS_DM:
1235 str = lcs_dm;
1236 break;
1237 case LCS_SD:
1238 str = lcs_sd;
1239 break;
1240 case LCS_SE:
1241 str = lcs_secure;
1242 break;
1243 case LCS_FA:
1244 str = lcs_fa;
1245 break;
1246 default:
1247 str = unknown;
1248 break;
1249 }
1250
1251 lcm_state:
1252 NOTICE("BL2: LCM state is %s\n", str);
1253
1254 rcar_avs_end();
1255 is_ddr_backup_mode();
1256
1257 bl2_tzram_layout.total_base = BL31_BASE;
1258 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE;
1259
1260 if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
1261 boot_cpu == MODEMR_BOOT_CPU_CA53) {
1262 ret = rcar_dram_init();
1263 if (ret) {
1264 NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
1265 panic();
1266 }
1267 rcar_qos_init();
1268 }
1269
1270 /* Set up FDT */
1271 ret = fdt_create_empty_tree(fdt, sizeof(fdt_blob));
1272 if (ret) {
1273 NOTICE("BL2: Cannot allocate FDT for U-Boot (ret=%i)\n", ret);
1274 panic();
1275 }
1276
1277 /* Add platform compatible string */
1278 bl2_populate_compatible_string(fdt);
1279
1280 /* Enable RPC if unlocked */
1281 bl2_add_rpc_node();
1282
1283 /* Print DRAM layout */
1284 bl2_advertise_dram_size(product);
1285
1286 /* Add KASLR seed */
1287 bl2_add_kaslr_seed();
1288
1289 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
1290 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8) {
1291 if (rcar_emmc_init() != EMMC_SUCCESS) {
1292 NOTICE("BL2: Failed to eMMC driver initialize.\n");
1293 panic();
1294 }
1295 rcar_emmc_memcard_power(EMMC_POWER_ON);
1296 if (rcar_emmc_mount() != EMMC_SUCCESS) {
1297 NOTICE("BL2: Failed to eMMC mount operation.\n");
1298 panic();
1299 }
1300 } else {
1301 rcar_rpc_init();
1302 rcar_dma_init();
1303 }
1304
1305 reg = mmio_read_32(RST_WDTRSTCR);
1306 reg &= ~WDTRSTCR_RWDT_RSTMSK;
1307 reg |= WDTRSTCR_PASSWORD;
1308 mmio_write_32(RST_WDTRSTCR, reg);
1309
1310 mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD);
1311 mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD);
1312
1313 reg = mmio_read_32(RCAR_PRR);
1314 if ((reg & RCAR_CPU_MASK_CA57) == RCAR_CPU_HAVE_CA57)
1315 mmio_write_32(CPG_CA57DBGRCR,
1316 DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR));
1317
1318 if ((reg & RCAR_CPU_MASK_CA53) == RCAR_CPU_HAVE_CA53)
1319 mmio_write_32(CPG_CA53DBGRCR,
1320 DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
1321
1322 if (product_cut == PRR_PRODUCT_H3_CUT10) {
1323 reg = mmio_read_32(CPG_PLL2CR);
1324 reg &= ~((uint32_t) 1 << 5);
1325 mmio_write_32(CPG_PLL2CR, reg);
1326
1327 reg = mmio_read_32(CPG_PLL4CR);
1328 reg &= ~((uint32_t) 1 << 5);
1329 mmio_write_32(CPG_PLL4CR, reg);
1330
1331 reg = mmio_read_32(CPG_PLL0CR);
1332 reg &= ~((uint32_t) 1 << 12);
1333 mmio_write_32(CPG_PLL0CR, reg);
1334 }
1335
1336 bl2_create_fcnl_reserved_memory();
1337
1338 fdt_pack(fdt);
1339 NOTICE("BL2: FDT at %p\n", fdt);
1340
1341 if (boot_dev == MODEMR_BOOT_DEV_EMMC_25X1 ||
1342 boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)
1343 rcar_io_emmc_setup();
1344 else
1345 rcar_io_setup();
1346 }
1347
bl2_plat_arch_setup(void)1348 void bl2_plat_arch_setup(void)
1349 {
1350 rcar_configure_mmu_el3(BL2_BASE,
1351 BL2_END - BL2_BASE,
1352 BL2_RO_BASE, BL2_RO_LIMIT
1353 #if USE_COHERENT_MEM
1354 , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
1355 #endif
1356 );
1357 }
1358
bl2_plat_prepare_exit(void)1359 void bl2_plat_prepare_exit(void)
1360 {
1361 bl2_ram_security_setting_finish();
1362 }
1363
bl2_platform_setup(void)1364 void bl2_platform_setup(void)
1365 {
1366
1367 }
1368
bl2_init_generic_timer(void)1369 static void bl2_init_generic_timer(void)
1370 {
1371 /* FIXME: V3M 16.666 MHz ? */
1372 #if RCAR_LSI == RCAR_D3
1373 uint32_t reg_cntfid = EXTAL_DRAAK;
1374 #elif RCAR_LSI == RCAR_E3
1375 uint32_t reg_cntfid = EXTAL_EBISU;
1376 #else /* RCAR_LSI == RCAR_E3 */
1377 uint32_t reg;
1378 uint32_t reg_cntfid;
1379 uint32_t modemr;
1380 uint32_t modemr_pll;
1381 uint32_t board_type;
1382 uint32_t board_rev;
1383 uint32_t pll_table[] = {
1384 EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */
1385 EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */
1386 EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */
1387 EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */
1388 };
1389
1390 modemr = mmio_read_32(RCAR_MODEMR);
1391 modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK);
1392
1393 /* Set frequency data in CNTFID0 */
1394 reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
1395 reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
1396 switch (modemr_pll) {
1397 case MD14_MD13_TYPE_0:
1398 rcar_get_board_type(&board_type, &board_rev);
1399 if (BOARD_SALVATOR_XS == board_type) {
1400 reg_cntfid = EXTAL_SALVATOR_XS;
1401 }
1402 break;
1403 case MD14_MD13_TYPE_3:
1404 if (PRR_PRODUCT_H3_CUT10 == reg) {
1405 reg_cntfid = reg_cntfid >> 1U;
1406 }
1407 break;
1408 default:
1409 /* none */
1410 break;
1411 }
1412 #endif /* RCAR_LSI == RCAR_E3 */
1413 /* Update memory mapped and register based frequency */
1414 write_cntfrq_el0((u_register_t )reg_cntfid);
1415 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
1416 /* Enable counter */
1417 mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF,
1418 (uint32_t)CNTCR_EN);
1419 }
1420