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Searched defs:cpu (Results 51 – 75 of 119) sorted by relevance

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/rk3399_ARM-atf/plat/mediatek/drivers/mcusys/v1/
H A Dmcucfg.h16 #define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_BASE + 0x2290 + ((cpu) * 8)) argument
17 #define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_BASE + 0x2294 + ((cpu) * 8)) argument
25 #define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) (MCUCFG_BASE + 0x1C30 + \ argument
63 #define GIC_WAKEUP_IGNORE(cpu) BIT(21 + cpu) argument
96 #define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x038 + ((cpu) * 8)) argument
107 #define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x238 + ((cpu) * 8)) argument
/rk3399_ARM-atf/plat/renesas/rcar_gen4/
H A Dplat_topology.c30 u_register_t cpu; in plat_core_pos_by_mpidr() local
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_psci_handlers.c55 uint32_t cpu = plat_my_core_pos(); in tegra_soc_validate_power_state() local
97 uint32_t cpu = plat_my_core_pos(); in tegra_soc_cpu_standby() local
247 uint32_t cpu = plat_my_core_pos(); in tegra_soc_get_target_pwr_state() local
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v2/
H A Dmcucfg.h45 #define CPC_CPU_LATENCY(cpu) (CPC_CPU0_LATENCY + 4 * (cpu)) argument
56 #define GIC_WAKEUP_IGNORE(cpu) BIT(21 + (cpu)) argument
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v1/
H A Dmcucfg.h15 #define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) \ argument
17 #define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) \ argument
50 #define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \ argument
108 #define CPC_CPU_LATENCY(cpu) (CPC_CPU0_LATENCY + 4 * (cpu)) argument
117 #define GIC_WAKEUP_IGNORE(cpu) BIT(21 + (cpu)) argument
153 #define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x038 + (cpu) * 8) argument
165 #define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MCUCFG_BASE + 0x238 + ((cpu) * 8)) argument
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_cpu_pm.c170 static unsigned int cpupm_cpu_ildo_state_valid(unsigned int cpu) in cpupm_cpu_ildo_state_valid()
203 unsigned int cpu = plat_my_core_pos(); in cpupm_cpu_retention_control() local
219 #define cpupm_cpu_ildo_state_valid(cpu) argument
245 static int cpupm_cpu_pwr_on_prepare(unsigned int cpu, uintptr_t entry) in cpupm_cpu_pwr_on_prepare()
297 static void cpupm_smp_init(unsigned int cpu, uintptr_t sec_entrypoint) in cpupm_smp_init()
487 uint32_t cpu = plat_my_core_pos(); in mcusys_prepare_resume() local
H A Dmt_cpu_pm_cpc.c38 struct mtk_cpc_lat_data cpu[PLATFORM_CORE_COUNT]; member
193 void mtk_cpc_core_on_hint_set(int cpu) in mtk_cpc_core_on_hint_set()
198 void mtk_cpc_core_on_hint_clr(int cpu) in mtk_cpc_core_on_hint_clr()
482 unsigned int cpu = 0; in mtk_cpu_pm_counter_clear() local
511 void mtk_cpu_pm_counter_update(unsigned int cpu) in mtk_cpu_pm_counter_update()
/rk3399_ARM-atf/plat/aspeed/ast2700/
H A Dplat_pm.c19 unsigned int cpu = plat_core_pos_by_mpidr(mpidr); in plat_pwr_domain_on() local
/rk3399_ARM-atf/plat/renesas/rcar_gen5/
H A Dplat_topology.c75 u_register_t cpu; in plat_core_pos_by_mpidr() local
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/pmu/
H A Dpmu.c168 uint32_t boot_cpu, cpu; in nonboot_cpus_off() local
298 uint32_t cpu; in plat_rockchip_pmu_init() local
/rk3399_ARM-atf/plat/mediatek/drivers/gicv3/
H A Dmt_gic_v3.c108 uint32_t cpu; in mt_gic_rdistif_save() local
120 uint32_t cpu; in mt_gic_rdistif_restore() local
/rk3399_ARM-atf/plat/allwinner/common/
H A Dsunxi_pm.c49 for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; ++cpu) { in plat_setup_psci_ops() local
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v3/
H A Dmcucfg.h45 #define CPC_CPU_LATENCY(cpu) (CPC_CPU0_LATENCY + 4 * (cpu)) argument
56 #define GIC_WAKEUP_IGNORE(cpu) BIT(21 + (cpu)) argument
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpmu.c62 static int check_cpu_wfie(uint32_t cpu) in check_cpu_wfie()
83 static inline uint32_t cpu_power_domain_st(uint32_t cpu) in cpu_power_domain_st()
89 static int cpu_power_domain_ctr(uint32_t cpu, uint32_t pd_state) in cpu_power_domain_ctr()
267 uint32_t boot_cpu, cpu; in nonboot_cpus_off() local
1023 int cpu; in plat_rockchip_pmu_init() local
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_cpu_pm_cpc.c107 void mtk_cpc_core_on_hint_set(int cpu) in mtk_cpc_core_on_hint_set()
112 void mtk_cpc_core_on_hint_clr(int cpu) in mtk_cpc_core_on_hint_clr()
H A Dmt_smp.c24 void mt_smp_core_init_arch(unsigned int cluster, unsigned int cpu, int arm64, in mt_smp_core_init_arch()
/rk3399_ARM-atf/plat/mediatek/mt8192/include/
H A Dmcucfg.h18 #define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8)) argument
19 #define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8)) argument
52 #define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \ argument
112 #define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MP0_MISC_CONFIG2 + ((cpu) * 8)) argument
125 #define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MP1_MISC_CONFIG2 + ((cpu) * 8)) argument
/rk3399_ARM-atf/plat/mediatek/mt8195/include/
H A Dmcucfg.h18 #define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8)) argument
19 #define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8)) argument
52 #define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \ argument
112 #define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MP0_MISC_CONFIG2 + ((cpu) * 8)) argument
125 #define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MP1_MISC_CONFIG2 + ((cpu) * 8)) argument
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dmcucfg.h18 #define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8)) argument
19 #define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8)) argument
52 #define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \ argument
111 #define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MP0_MISC_CONFIG2 + ((cpu) * 8)) argument
124 #define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MP1_MISC_CONFIG2 + ((cpu) * 8)) argument
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/mcdi/
H A Dmt_cpu_pm_cpc.c122 void mtk_cpc_core_on_hint_set(unsigned int cpu) in mtk_cpc_core_on_hint_set()
127 void mtk_cpc_core_on_hint_clr(unsigned int cpu) in mtk_cpc_core_on_hint_clr()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/mcdi/
H A Dmt_cpu_pm_cpc.c122 void mtk_cpc_core_on_hint_set(unsigned int cpu) in mtk_cpc_core_on_hint_set()
127 void mtk_cpc_core_on_hint_clr(unsigned int cpu) in mtk_cpc_core_on_hint_clr()
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/mcdi/
H A Dmt_cpu_pm_cpc.c122 void mtk_cpc_core_on_hint_set(unsigned int cpu) in mtk_cpc_core_on_hint_set()
127 void mtk_cpc_core_on_hint_clr(unsigned int cpu) in mtk_cpc_core_on_hint_clr()
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spmc/
H A Dmtspmc_private.h25 #define per_cpu(cluster, cpu, reg) \ argument
118 #define MCUCFG_INITARCH_CPU_BIT(cpu) BIT(16U + cpu) argument
126 #define GIC_WAKEUP_IGNORE(cpu) BIT(21 + cpu) argument
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spmc/
H A Dmtspmc_private.h27 #define per_cpu(cluster, cpu, reg) \ argument
124 #define MCUCFG_INITARCH_CPU_BIT(cpu) BIT(16U + cpu) argument
133 #define GIC_WAKEUP_IGNORE(cpu) BIT(21 + cpu) argument
/rk3399_ARM-atf/drivers/renesas/common/pwrc/
H A Dpwrc.c156 uint64_t cm, cpu; in rcar_pwrc_status() local
245 uint64_t cpu; in rcar_pwrc_cpuon() local
269 uint64_t cpu; in rcar_pwrc_cpuoff() local
290 uint64_t cpu; in rcar_pwrc_enable_interrupt_wakeup() local
310 uint64_t cpu; in rcar_pwrc_disable_interrupt_wakeup() local
329 u_register_t cl, cpu, mpidr; in rcar_pwrc_all_disable_interrupt_wakeup() local

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