1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * CPPC (Collaborative Processor Performance Control) driver for
4*4882a593Smuzhiyun * interfacing with the CPUfreq layer and governors. See
5*4882a593Smuzhiyun * cppc_acpi.c for CPPC specific methods.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * (C) Copyright 2014, 2015 Linaro Ltd.
8*4882a593Smuzhiyun * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define pr_fmt(fmt) "CPPC Cpufreq:" fmt
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/cpu.h>
17*4882a593Smuzhiyun #include <linux/cpufreq.h>
18*4882a593Smuzhiyun #include <linux/dmi.h>
19*4882a593Smuzhiyun #include <linux/time.h>
20*4882a593Smuzhiyun #include <linux/vmalloc.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <asm/unaligned.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include <acpi/cppc_acpi.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Minimum struct length needed for the DMI processor entry we want */
27*4882a593Smuzhiyun #define DMI_ENTRY_PROCESSOR_MIN_LENGTH 48
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* Offest in the DMI processor structure for the max frequency */
30*4882a593Smuzhiyun #define DMI_PROCESSOR_MAX_SPEED 0x14
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * These structs contain information parsed from per CPU
34*4882a593Smuzhiyun * ACPI _CPC structures.
35*4882a593Smuzhiyun * e.g. For each CPU the highest, lowest supported
36*4882a593Smuzhiyun * performance capabilities, desired performance level
37*4882a593Smuzhiyun * requested etc.
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun static struct cppc_cpudata **all_cpu_data;
40*4882a593Smuzhiyun static bool boost_supported;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun struct cppc_workaround_oem_info {
43*4882a593Smuzhiyun char oem_id[ACPI_OEM_ID_SIZE + 1];
44*4882a593Smuzhiyun char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
45*4882a593Smuzhiyun u32 oem_revision;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun static struct cppc_workaround_oem_info wa_info[] = {
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun .oem_id = "HISI ",
51*4882a593Smuzhiyun .oem_table_id = "HIP07 ",
52*4882a593Smuzhiyun .oem_revision = 0,
53*4882a593Smuzhiyun }, {
54*4882a593Smuzhiyun .oem_id = "HISI ",
55*4882a593Smuzhiyun .oem_table_id = "HIP08 ",
56*4882a593Smuzhiyun .oem_revision = 0,
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Callback function used to retrieve the max frequency from DMI */
cppc_find_dmi_mhz(const struct dmi_header * dm,void * private)61*4882a593Smuzhiyun static void cppc_find_dmi_mhz(const struct dmi_header *dm, void *private)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun const u8 *dmi_data = (const u8 *)dm;
64*4882a593Smuzhiyun u16 *mhz = (u16 *)private;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun if (dm->type == DMI_ENTRY_PROCESSOR &&
67*4882a593Smuzhiyun dm->length >= DMI_ENTRY_PROCESSOR_MIN_LENGTH) {
68*4882a593Smuzhiyun u16 val = (u16)get_unaligned((const u16 *)
69*4882a593Smuzhiyun (dmi_data + DMI_PROCESSOR_MAX_SPEED));
70*4882a593Smuzhiyun *mhz = val > *mhz ? val : *mhz;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Look up the max frequency in DMI */
cppc_get_dmi_max_khz(void)75*4882a593Smuzhiyun static u64 cppc_get_dmi_max_khz(void)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun u16 mhz = 0;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun dmi_walk(cppc_find_dmi_mhz, &mhz);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /*
82*4882a593Smuzhiyun * Real stupid fallback value, just in case there is no
83*4882a593Smuzhiyun * actual value set.
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun mhz = mhz ? mhz : 1;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return (1000 * mhz);
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun * If CPPC lowest_freq and nominal_freq registers are exposed then we can
92*4882a593Smuzhiyun * use them to convert perf to freq and vice versa
93*4882a593Smuzhiyun *
94*4882a593Smuzhiyun * If the perf/freq point lies between Nominal and Lowest, we can treat
95*4882a593Smuzhiyun * (Low perf, Low freq) and (Nom Perf, Nom freq) as 2D co-ordinates of a line
96*4882a593Smuzhiyun * and extrapolate the rest
97*4882a593Smuzhiyun * For perf/freq > Nominal, we use the ratio perf:freq at Nominal for conversion
98*4882a593Smuzhiyun */
cppc_cpufreq_perf_to_khz(struct cppc_cpudata * cpu,unsigned int perf)99*4882a593Smuzhiyun static unsigned int cppc_cpufreq_perf_to_khz(struct cppc_cpudata *cpu,
100*4882a593Smuzhiyun unsigned int perf)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun static u64 max_khz;
103*4882a593Smuzhiyun struct cppc_perf_caps *caps = &cpu->perf_caps;
104*4882a593Smuzhiyun u64 mul, div;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun if (caps->lowest_freq && caps->nominal_freq) {
107*4882a593Smuzhiyun if (perf >= caps->nominal_perf) {
108*4882a593Smuzhiyun mul = caps->nominal_freq;
109*4882a593Smuzhiyun div = caps->nominal_perf;
110*4882a593Smuzhiyun } else {
111*4882a593Smuzhiyun mul = caps->nominal_freq - caps->lowest_freq;
112*4882a593Smuzhiyun div = caps->nominal_perf - caps->lowest_perf;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun } else {
115*4882a593Smuzhiyun if (!max_khz)
116*4882a593Smuzhiyun max_khz = cppc_get_dmi_max_khz();
117*4882a593Smuzhiyun mul = max_khz;
118*4882a593Smuzhiyun div = caps->highest_perf;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun return (u64)perf * mul / div;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
cppc_cpufreq_khz_to_perf(struct cppc_cpudata * cpu,unsigned int freq)123*4882a593Smuzhiyun static unsigned int cppc_cpufreq_khz_to_perf(struct cppc_cpudata *cpu,
124*4882a593Smuzhiyun unsigned int freq)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun static u64 max_khz;
127*4882a593Smuzhiyun struct cppc_perf_caps *caps = &cpu->perf_caps;
128*4882a593Smuzhiyun u64 mul, div;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun if (caps->lowest_freq && caps->nominal_freq) {
131*4882a593Smuzhiyun if (freq >= caps->nominal_freq) {
132*4882a593Smuzhiyun mul = caps->nominal_perf;
133*4882a593Smuzhiyun div = caps->nominal_freq;
134*4882a593Smuzhiyun } else {
135*4882a593Smuzhiyun mul = caps->lowest_perf;
136*4882a593Smuzhiyun div = caps->lowest_freq;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun } else {
139*4882a593Smuzhiyun if (!max_khz)
140*4882a593Smuzhiyun max_khz = cppc_get_dmi_max_khz();
141*4882a593Smuzhiyun mul = caps->highest_perf;
142*4882a593Smuzhiyun div = max_khz;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun return (u64)freq * mul / div;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
cppc_cpufreq_set_target(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int relation)148*4882a593Smuzhiyun static int cppc_cpufreq_set_target(struct cpufreq_policy *policy,
149*4882a593Smuzhiyun unsigned int target_freq,
150*4882a593Smuzhiyun unsigned int relation)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun struct cppc_cpudata *cpu;
153*4882a593Smuzhiyun struct cpufreq_freqs freqs;
154*4882a593Smuzhiyun u32 desired_perf;
155*4882a593Smuzhiyun int ret = 0;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun cpu = all_cpu_data[policy->cpu];
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun desired_perf = cppc_cpufreq_khz_to_perf(cpu, target_freq);
160*4882a593Smuzhiyun /* Return if it is exactly the same perf */
161*4882a593Smuzhiyun if (desired_perf == cpu->perf_ctrls.desired_perf)
162*4882a593Smuzhiyun return ret;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun cpu->perf_ctrls.desired_perf = desired_perf;
165*4882a593Smuzhiyun freqs.old = policy->cur;
166*4882a593Smuzhiyun freqs.new = target_freq;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun cpufreq_freq_transition_begin(policy, &freqs);
169*4882a593Smuzhiyun ret = cppc_set_perf(cpu->cpu, &cpu->perf_ctrls);
170*4882a593Smuzhiyun cpufreq_freq_transition_end(policy, &freqs, ret != 0);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun if (ret)
173*4882a593Smuzhiyun pr_debug("Failed to set target on CPU:%d. ret:%d\n",
174*4882a593Smuzhiyun cpu->cpu, ret);
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun return ret;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
cppc_verify_policy(struct cpufreq_policy_data * policy)179*4882a593Smuzhiyun static int cppc_verify_policy(struct cpufreq_policy_data *policy)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun cpufreq_verify_within_cpu_limits(policy);
182*4882a593Smuzhiyun return 0;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
cppc_cpufreq_stop_cpu(struct cpufreq_policy * policy)185*4882a593Smuzhiyun static void cppc_cpufreq_stop_cpu(struct cpufreq_policy *policy)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun int cpu_num = policy->cpu;
188*4882a593Smuzhiyun struct cppc_cpudata *cpu = all_cpu_data[cpu_num];
189*4882a593Smuzhiyun int ret;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun cpu->perf_ctrls.desired_perf = cpu->perf_caps.lowest_perf;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls);
194*4882a593Smuzhiyun if (ret)
195*4882a593Smuzhiyun pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n",
196*4882a593Smuzhiyun cpu->perf_caps.lowest_perf, cpu_num, ret);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /*
200*4882a593Smuzhiyun * The PCC subspace describes the rate at which platform can accept commands
201*4882a593Smuzhiyun * on the shared PCC channel (including READs which do not count towards freq
202*4882a593Smuzhiyun * trasition requests), so ideally we need to use the PCC values as a fallback
203*4882a593Smuzhiyun * if we don't have a platform specific transition_delay_us
204*4882a593Smuzhiyun */
205*4882a593Smuzhiyun #ifdef CONFIG_ARM64
206*4882a593Smuzhiyun #include <asm/cputype.h>
207*4882a593Smuzhiyun
cppc_cpufreq_get_transition_delay_us(int cpu)208*4882a593Smuzhiyun static unsigned int cppc_cpufreq_get_transition_delay_us(int cpu)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun unsigned long implementor = read_cpuid_implementor();
211*4882a593Smuzhiyun unsigned long part_num = read_cpuid_part_number();
212*4882a593Smuzhiyun unsigned int delay_us = 0;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun switch (implementor) {
215*4882a593Smuzhiyun case ARM_CPU_IMP_QCOM:
216*4882a593Smuzhiyun switch (part_num) {
217*4882a593Smuzhiyun case QCOM_CPU_PART_FALKOR_V1:
218*4882a593Smuzhiyun case QCOM_CPU_PART_FALKOR:
219*4882a593Smuzhiyun delay_us = 10000;
220*4882a593Smuzhiyun break;
221*4882a593Smuzhiyun default:
222*4882a593Smuzhiyun delay_us = cppc_get_transition_latency(cpu) / NSEC_PER_USEC;
223*4882a593Smuzhiyun break;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun break;
226*4882a593Smuzhiyun default:
227*4882a593Smuzhiyun delay_us = cppc_get_transition_latency(cpu) / NSEC_PER_USEC;
228*4882a593Smuzhiyun break;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun return delay_us;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun #else
235*4882a593Smuzhiyun
cppc_cpufreq_get_transition_delay_us(int cpu)236*4882a593Smuzhiyun static unsigned int cppc_cpufreq_get_transition_delay_us(int cpu)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun return cppc_get_transition_latency(cpu) / NSEC_PER_USEC;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun #endif
241*4882a593Smuzhiyun
cppc_cpufreq_cpu_init(struct cpufreq_policy * policy)242*4882a593Smuzhiyun static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun struct cppc_cpudata *cpu;
245*4882a593Smuzhiyun unsigned int cpu_num = policy->cpu;
246*4882a593Smuzhiyun int ret = 0;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun cpu = all_cpu_data[policy->cpu];
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun cpu->cpu = cpu_num;
251*4882a593Smuzhiyun ret = cppc_get_perf_caps(policy->cpu, &cpu->perf_caps);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun if (ret) {
254*4882a593Smuzhiyun pr_debug("Err reading CPU%d perf capabilities. ret:%d\n",
255*4882a593Smuzhiyun cpu_num, ret);
256*4882a593Smuzhiyun return ret;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun /* Convert the lowest and nominal freq from MHz to KHz */
260*4882a593Smuzhiyun cpu->perf_caps.lowest_freq *= 1000;
261*4882a593Smuzhiyun cpu->perf_caps.nominal_freq *= 1000;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun /*
264*4882a593Smuzhiyun * Set min to lowest nonlinear perf to avoid any efficiency penalty (see
265*4882a593Smuzhiyun * Section 8.4.7.1.1.5 of ACPI 6.1 spec)
266*4882a593Smuzhiyun */
267*4882a593Smuzhiyun policy->min = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.lowest_nonlinear_perf);
268*4882a593Smuzhiyun policy->max = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.nominal_perf);
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun /*
271*4882a593Smuzhiyun * Set cpuinfo.min_freq to Lowest to make the full range of performance
272*4882a593Smuzhiyun * available if userspace wants to use any perf between lowest & lowest
273*4882a593Smuzhiyun * nonlinear perf
274*4882a593Smuzhiyun */
275*4882a593Smuzhiyun policy->cpuinfo.min_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.lowest_perf);
276*4882a593Smuzhiyun policy->cpuinfo.max_freq = cppc_cpufreq_perf_to_khz(cpu, cpu->perf_caps.nominal_perf);
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun policy->transition_delay_us = cppc_cpufreq_get_transition_delay_us(cpu_num);
279*4882a593Smuzhiyun policy->shared_type = cpu->shared_type;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) {
282*4882a593Smuzhiyun int i;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun cpumask_copy(policy->cpus, cpu->shared_cpu_map);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun for_each_cpu(i, policy->cpus) {
287*4882a593Smuzhiyun if (unlikely(i == policy->cpu))
288*4882a593Smuzhiyun continue;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun memcpy(&all_cpu_data[i]->perf_caps, &cpu->perf_caps,
291*4882a593Smuzhiyun sizeof(cpu->perf_caps));
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun } else if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL) {
294*4882a593Smuzhiyun /* Support only SW_ANY for now. */
295*4882a593Smuzhiyun pr_debug("Unsupported CPU co-ord type\n");
296*4882a593Smuzhiyun return -EFAULT;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun cpu->cur_policy = policy;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun /*
302*4882a593Smuzhiyun * If 'highest_perf' is greater than 'nominal_perf', we assume CPU Boost
303*4882a593Smuzhiyun * is supported.
304*4882a593Smuzhiyun */
305*4882a593Smuzhiyun if (cpu->perf_caps.highest_perf > cpu->perf_caps.nominal_perf)
306*4882a593Smuzhiyun boost_supported = true;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /* Set policy->cur to max now. The governors will adjust later. */
309*4882a593Smuzhiyun policy->cur = cppc_cpufreq_perf_to_khz(cpu,
310*4882a593Smuzhiyun cpu->perf_caps.highest_perf);
311*4882a593Smuzhiyun cpu->perf_ctrls.desired_perf = cpu->perf_caps.highest_perf;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls);
314*4882a593Smuzhiyun if (ret)
315*4882a593Smuzhiyun pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n",
316*4882a593Smuzhiyun cpu->perf_caps.highest_perf, cpu_num, ret);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun return ret;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
get_delta(u64 t1,u64 t0)321*4882a593Smuzhiyun static inline u64 get_delta(u64 t1, u64 t0)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun if (t1 > t0 || t0 > ~(u32)0)
324*4882a593Smuzhiyun return t1 - t0;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun return (u32)t1 - (u32)t0;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
cppc_get_rate_from_fbctrs(struct cppc_cpudata * cpu,struct cppc_perf_fb_ctrs fb_ctrs_t0,struct cppc_perf_fb_ctrs fb_ctrs_t1)329*4882a593Smuzhiyun static int cppc_get_rate_from_fbctrs(struct cppc_cpudata *cpu,
330*4882a593Smuzhiyun struct cppc_perf_fb_ctrs fb_ctrs_t0,
331*4882a593Smuzhiyun struct cppc_perf_fb_ctrs fb_ctrs_t1)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun u64 delta_reference, delta_delivered;
334*4882a593Smuzhiyun u64 reference_perf, delivered_perf;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun reference_perf = fb_ctrs_t0.reference_perf;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun delta_reference = get_delta(fb_ctrs_t1.reference,
339*4882a593Smuzhiyun fb_ctrs_t0.reference);
340*4882a593Smuzhiyun delta_delivered = get_delta(fb_ctrs_t1.delivered,
341*4882a593Smuzhiyun fb_ctrs_t0.delivered);
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun /* Check to avoid divide-by zero */
344*4882a593Smuzhiyun if (delta_reference || delta_delivered)
345*4882a593Smuzhiyun delivered_perf = (reference_perf * delta_delivered) /
346*4882a593Smuzhiyun delta_reference;
347*4882a593Smuzhiyun else
348*4882a593Smuzhiyun delivered_perf = cpu->perf_ctrls.desired_perf;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun return cppc_cpufreq_perf_to_khz(cpu, delivered_perf);
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun
cppc_cpufreq_get_rate(unsigned int cpunum)353*4882a593Smuzhiyun static unsigned int cppc_cpufreq_get_rate(unsigned int cpunum)
354*4882a593Smuzhiyun {
355*4882a593Smuzhiyun struct cppc_perf_fb_ctrs fb_ctrs_t0 = {0}, fb_ctrs_t1 = {0};
356*4882a593Smuzhiyun struct cppc_cpudata *cpu = all_cpu_data[cpunum];
357*4882a593Smuzhiyun int ret;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun ret = cppc_get_perf_ctrs(cpunum, &fb_ctrs_t0);
360*4882a593Smuzhiyun if (ret)
361*4882a593Smuzhiyun return ret;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun udelay(2); /* 2usec delay between sampling */
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun ret = cppc_get_perf_ctrs(cpunum, &fb_ctrs_t1);
366*4882a593Smuzhiyun if (ret)
367*4882a593Smuzhiyun return ret;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun return cppc_get_rate_from_fbctrs(cpu, fb_ctrs_t0, fb_ctrs_t1);
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun
cppc_cpufreq_set_boost(struct cpufreq_policy * policy,int state)372*4882a593Smuzhiyun static int cppc_cpufreq_set_boost(struct cpufreq_policy *policy, int state)
373*4882a593Smuzhiyun {
374*4882a593Smuzhiyun struct cppc_cpudata *cpudata;
375*4882a593Smuzhiyun int ret;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun if (!boost_supported) {
378*4882a593Smuzhiyun pr_err("BOOST not supported by CPU or firmware\n");
379*4882a593Smuzhiyun return -EINVAL;
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun cpudata = all_cpu_data[policy->cpu];
383*4882a593Smuzhiyun if (state)
384*4882a593Smuzhiyun policy->max = cppc_cpufreq_perf_to_khz(cpudata,
385*4882a593Smuzhiyun cpudata->perf_caps.highest_perf);
386*4882a593Smuzhiyun else
387*4882a593Smuzhiyun policy->max = cppc_cpufreq_perf_to_khz(cpudata,
388*4882a593Smuzhiyun cpudata->perf_caps.nominal_perf);
389*4882a593Smuzhiyun policy->cpuinfo.max_freq = policy->max;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun ret = freq_qos_update_request(policy->max_freq_req, policy->max);
392*4882a593Smuzhiyun if (ret < 0)
393*4882a593Smuzhiyun return ret;
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun return 0;
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun static struct cpufreq_driver cppc_cpufreq_driver = {
399*4882a593Smuzhiyun .flags = CPUFREQ_CONST_LOOPS,
400*4882a593Smuzhiyun .verify = cppc_verify_policy,
401*4882a593Smuzhiyun .target = cppc_cpufreq_set_target,
402*4882a593Smuzhiyun .get = cppc_cpufreq_get_rate,
403*4882a593Smuzhiyun .init = cppc_cpufreq_cpu_init,
404*4882a593Smuzhiyun .stop_cpu = cppc_cpufreq_stop_cpu,
405*4882a593Smuzhiyun .set_boost = cppc_cpufreq_set_boost,
406*4882a593Smuzhiyun .name = "cppc_cpufreq",
407*4882a593Smuzhiyun };
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun /*
410*4882a593Smuzhiyun * HISI platform does not support delivered performance counter and
411*4882a593Smuzhiyun * reference performance counter. It can calculate the performance using the
412*4882a593Smuzhiyun * platform specific mechanism. We reuse the desired performance register to
413*4882a593Smuzhiyun * store the real performance calculated by the platform.
414*4882a593Smuzhiyun */
hisi_cppc_cpufreq_get_rate(unsigned int cpunum)415*4882a593Smuzhiyun static unsigned int hisi_cppc_cpufreq_get_rate(unsigned int cpunum)
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun struct cppc_cpudata *cpudata = all_cpu_data[cpunum];
418*4882a593Smuzhiyun u64 desired_perf;
419*4882a593Smuzhiyun int ret;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun ret = cppc_get_desired_perf(cpunum, &desired_perf);
422*4882a593Smuzhiyun if (ret < 0)
423*4882a593Smuzhiyun return -EIO;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun return cppc_cpufreq_perf_to_khz(cpudata, desired_perf);
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun
cppc_check_hisi_workaround(void)428*4882a593Smuzhiyun static void cppc_check_hisi_workaround(void)
429*4882a593Smuzhiyun {
430*4882a593Smuzhiyun struct acpi_table_header *tbl;
431*4882a593Smuzhiyun acpi_status status = AE_OK;
432*4882a593Smuzhiyun int i;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun status = acpi_get_table(ACPI_SIG_PCCT, 0, &tbl);
435*4882a593Smuzhiyun if (ACPI_FAILURE(status) || !tbl)
436*4882a593Smuzhiyun return;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(wa_info); i++) {
439*4882a593Smuzhiyun if (!memcmp(wa_info[i].oem_id, tbl->oem_id, ACPI_OEM_ID_SIZE) &&
440*4882a593Smuzhiyun !memcmp(wa_info[i].oem_table_id, tbl->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
441*4882a593Smuzhiyun wa_info[i].oem_revision == tbl->oem_revision) {
442*4882a593Smuzhiyun /* Overwrite the get() callback */
443*4882a593Smuzhiyun cppc_cpufreq_driver.get = hisi_cppc_cpufreq_get_rate;
444*4882a593Smuzhiyun break;
445*4882a593Smuzhiyun }
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun acpi_put_table(tbl);
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun
cppc_cpufreq_init(void)451*4882a593Smuzhiyun static int __init cppc_cpufreq_init(void)
452*4882a593Smuzhiyun {
453*4882a593Smuzhiyun int i, ret = 0;
454*4882a593Smuzhiyun struct cppc_cpudata *cpu;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun if (acpi_disabled)
457*4882a593Smuzhiyun return -ENODEV;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun all_cpu_data = kcalloc(num_possible_cpus(), sizeof(void *),
460*4882a593Smuzhiyun GFP_KERNEL);
461*4882a593Smuzhiyun if (!all_cpu_data)
462*4882a593Smuzhiyun return -ENOMEM;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun for_each_possible_cpu(i) {
465*4882a593Smuzhiyun all_cpu_data[i] = kzalloc(sizeof(struct cppc_cpudata), GFP_KERNEL);
466*4882a593Smuzhiyun if (!all_cpu_data[i])
467*4882a593Smuzhiyun goto out;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun cpu = all_cpu_data[i];
470*4882a593Smuzhiyun if (!zalloc_cpumask_var(&cpu->shared_cpu_map, GFP_KERNEL))
471*4882a593Smuzhiyun goto out;
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun ret = acpi_get_psd_map(all_cpu_data);
475*4882a593Smuzhiyun if (ret) {
476*4882a593Smuzhiyun pr_debug("Error parsing PSD data. Aborting cpufreq registration.\n");
477*4882a593Smuzhiyun goto out;
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun cppc_check_hisi_workaround();
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun ret = cpufreq_register_driver(&cppc_cpufreq_driver);
483*4882a593Smuzhiyun if (ret)
484*4882a593Smuzhiyun goto out;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun return ret;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun out:
489*4882a593Smuzhiyun for_each_possible_cpu(i) {
490*4882a593Smuzhiyun cpu = all_cpu_data[i];
491*4882a593Smuzhiyun if (!cpu)
492*4882a593Smuzhiyun break;
493*4882a593Smuzhiyun free_cpumask_var(cpu->shared_cpu_map);
494*4882a593Smuzhiyun kfree(cpu);
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun kfree(all_cpu_data);
498*4882a593Smuzhiyun return -ENODEV;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun
cppc_cpufreq_exit(void)501*4882a593Smuzhiyun static void __exit cppc_cpufreq_exit(void)
502*4882a593Smuzhiyun {
503*4882a593Smuzhiyun struct cppc_cpudata *cpu;
504*4882a593Smuzhiyun int i;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun cpufreq_unregister_driver(&cppc_cpufreq_driver);
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun for_each_possible_cpu(i) {
509*4882a593Smuzhiyun cpu = all_cpu_data[i];
510*4882a593Smuzhiyun free_cpumask_var(cpu->shared_cpu_map);
511*4882a593Smuzhiyun kfree(cpu);
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun kfree(all_cpu_data);
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun module_exit(cppc_cpufreq_exit);
518*4882a593Smuzhiyun MODULE_AUTHOR("Ashwin Chaugule");
519*4882a593Smuzhiyun MODULE_DESCRIPTION("CPUFreq driver based on the ACPI CPPC v5.0+ spec");
520*4882a593Smuzhiyun MODULE_LICENSE("GPL");
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun late_initcall(cppc_cpufreq_init);
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun static const struct acpi_device_id cppc_acpi_ids[] __used = {
525*4882a593Smuzhiyun {ACPI_PROCESSOR_DEVICE_HID, },
526*4882a593Smuzhiyun {}
527*4882a593Smuzhiyun };
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, cppc_acpi_ids);
530