| /utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/ |
| H A D | mvideo_context.h | 561 MS_PHY u32BWR_Miu_Right_OPMBase1; member
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_sc.c | 6036 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address() 6037 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address() 6170 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address_burst() 6171 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address_burst()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_sc.c | 6173 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address() 6174 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address() 6307 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address_burst() 6308 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address_burst()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_sc.c | 7275 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address() 7276 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address() 7410 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address_burst() 7411 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address_burst()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_sc.c | 7883 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address() 7884 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address() 8066 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address_burst() 8067 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address_burst()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_sc.c | 8086 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address() 8087 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address() 8224 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address_burst() 8225 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address_burst()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_sc.c | 8783 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address() 8784 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address() 8961 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address_burst() 8962 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address_burst()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_sc.c | 8806 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address() 8807 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address() 8945 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address_burst() 8946 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address_burst()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_sc.c | 9064 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address() 9065 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address() 9242 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address_burst() 9243 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address_burst()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_sc.c | 9065 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address() 9066 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address() 9203 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0x… in _HAL_SC_BWR_set_base_address_burst() 9204 …x * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x… in _HAL_SC_BWR_set_base_address_burst()
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| /utopia/UTPA2-700.0.x/modules/xc/drv/xc/ |
| H A D | mdrv_sc_scaling.c | 9470 pSrcInfo->Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1 = u32OPMBase1; in _MDrv_SC_set_fetch_number_limit_impl() 9493 pSrcInfo->Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1 = u32OPMBase1; in _MDrv_SC_set_fetch_number_limit_impl()
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| H A D | mdrv_sc_scaling.c.0 | 9441 pSrcInfo->Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1 = u32OPMBase1; 9464 pSrcInfo->Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1 = u32OPMBase1;
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