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Searched refs:interlace (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/gpd/drv/gpd/
H A Dpngprocess.c685 infoptr->interlace = *(addr+12); in handle_IHDR()
1197 if (infoptr->interlace) in PngProcess()
1273 drv_gpd_set_type(PNG_COLOR_TYPE_RGB_ALPHA, infoptr->interlace, infoptr->color_depth); in PngProcess()
1289 drv_gpd_set_type(infoptr->color_type, infoptr->interlace, infoptr->color_depth); in PngProcess()
1293 if(infoptr->interlace) in PngProcess()
H A Ddrvgpd.c599 void drv_gpd_set_interlace(MS_U8 interlace) in drv_gpd_set_interlace() argument
601 if (interlace) in drv_gpd_set_interlace()
804 void drv_gpd_set_type(MS_U8 color_type, MS_U8 interlace, MS_U8 color_depth) in drv_gpd_set_type() argument
807 GPD_SET_MS_U32REG(reg_gpd_interlace, interlace); in drv_gpd_set_type()
H A Ddrvgpd.h141 void drv_gpd_set_interlace(MS_U8 interlace);
152 void drv_gpd_set_type(MS_U8 color_type, MS_U8 interlace, MS_U8 color_depth);
H A Dmdrvgpd.c220 pic_info->u8Interlace = pnginfo->interlace; in mdrv_gpd_decode()
H A Dpng.h599 MS_U8 interlace,compression,filter; member
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dmhal_xc_chip_config.h.0355 //hw support 2 line mode deinterlace for interlace or not
395 //device 1 is interlace out
404 // if H/W support interlace output timing
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_sc_scaling.c.01794 // for interlace, keep y in multiple of 2
2052 // 1. mirror+freerun (P mode. eg 25p,30p), at least 3 frames (interlace mode have no this limitat…
2055 // 4. non-mirror+uc (P mode), at least 3 frames (interlace mode only need 4 field, eg. 25_4R_MC)
2161 //when pip/pop + no mirror, need use 3 or more frames mode(for interlace, 6 fields or above)
2162 //when pip/pop + mirror, need use 4 or more frames mode(for interlace, 8 fields or above)
2728 …/HAL_SC_Enable_VInitFactor(FALSE,eWindow);//Let AP layer to decide enable/dsiable for FBL interlace
2873 // if SC1 is interlace out, two init factor mode is used for P2I.
4484 //mirror and sub window: progressive: 4 frame mode; interlace: 8 field mode
4485 //sub window: progressive: 3 frame mode; interlace: 6 field mode
4486 //input vfreq > panel supported vfreq: progressive: 3 frame mode; interlace: 6 field mode
[all …]
H A Dmvideo.c.02719 …reg_IP1F2_21 = 0x0101;//IP1 sometimes will detect opcapture to interlace,we force it to progressive
2834 //IP1 sometimes will detect opcapture to interlace,we force it to progressive
2935 //IP1 sometimes will detect opcapture to interlace,we force it to progressive
2957 //IP1 sometimes will detect opcapture to interlace,we force it to progressive
3478 … // If memory format is PX2 progressive mode, set to use interlace line buffer setting
4976 #if VERIFY_MVIDEO_FPGA //non-de-interlace function
5496 #if VERIFY_MVIDEO_FPGA //non-de-interlace function=> celear second frame half garbage
H A Dmdrv_sc_display.c.03199 // no matter progressive or interlace
3200 // in FB mode we set to 0x5 (originally progressive = 0x3, interlace = 0x4)
/utopia/UTPA2-700.0.x/modules/xc/api/xc/
H A DapiXC_PCMonitor.c.0316 // Old Patch Method: Force interlace
/utopia/UTPA2-700.0.x/modules/vdec_v3/api/vdec_v3/
H A DapiVDEC_EX.c.06110 /// Force into interlace mode
13253 pDispinfo->u8Interlace = 0; // no interlace