Home
last modified time | relevance | path

Searched refs:__BIT4 (Results 1 – 25 of 90) sorted by relevance

1234

/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6lite/hwi2c/
H A DregHWI2C.h153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
173 #define _MIIC_CFG_EN_TMTINT (__BIT4)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
197 #define _INT_CLKSTR (__BIT4)
214 #define _DMA_CFG_MIUPRI (__BIT4)
256 #define _MIIC_CFG_EN_TMTINT (__BIT4)
274 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
280 #define _INT_CLKSTR (__BIT4)
297 #define _DMA_CFG_MIUPRI (__BIT4)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/kano/hwi2c/
H A DregHWI2C.h153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
173 #define _MIIC_CFG_EN_TMTINT (__BIT4)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
197 #define _INT_CLKSTR (__BIT4)
214 #define _DMA_CFG_MIUPRI (__BIT4)
256 #define _MIIC_CFG_EN_TMTINT (__BIT4)
274 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
280 #define _INT_CLKSTR (__BIT4)
297 #define _DMA_CFG_MIUPRI (__BIT4)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6/hwi2c/
H A DregHWI2C.h153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
173 #define _MIIC_CFG_EN_TMTINT (__BIT4)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
197 #define _INT_CLKSTR (__BIT4)
214 #define _DMA_CFG_MIUPRI (__BIT4)
256 #define _MIIC_CFG_EN_TMTINT (__BIT4)
274 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
280 #define _INT_CLKSTR (__BIT4)
297 #define _DMA_CFG_MIUPRI (__BIT4)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/curry/hwi2c/
H A DregHWI2C.h153 #define CHIP_REG_HWI2C_MIIC1_CLK_MSK (__BIT4 | __BIT5 | __BIT6 | __BIT7)
173 #define _MIIC_CFG_EN_TMTINT (__BIT4)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
197 #define _INT_CLKSTR (__BIT4)
214 #define _DMA_CFG_MIUPRI (__BIT4)
256 #define _MIIC_CFG_EN_TMTINT (__BIT4)
274 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
280 #define _INT_CLKSTR (__BIT4)
297 #define _DMA_CFG_MIUPRI (__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/maldives/pm/
H A DhalPM.c355 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
592 HAL_PM_WriteByte(0x2e53,HAL_PM_ReadByte(0x2e53)&(~__BIT4)); //8051 reset in HAL_PM_SetSRAMOffsetForMCU()
624 HAL_PM_WriteByte(0x2e53,HAL_PM_ReadByte(0x2e53)|__BIT4); //release 8051 reset in HAL_PM_SetSRAMOffsetForMCU()
639 HAL_PM_WriteByte(0x2e53,HAL_PM_ReadByte(0x2e53)&(~__BIT4)); //8051 reset in HAL_PM_SetDRAMOffsetForMCU()
673 HAL_PM_WriteByte(0x2e53,HAL_PM_ReadByte(0x2e53)|__BIT4); //release 8051 reset in HAL_PM_SetDRAMOffsetForMCU()
744 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
772 HAL_PM_Write2Byte(REG_PM_GPIO4_OUT, (HAL_PM_Read2Byte(REG_PM_GPIO4_OUT))|(__BIT4)); in HAL_PM_GPIO4_SetPower()
773 HAL_PM_Write2Byte(REG_PM_GPIO4_OEN, (HAL_PM_Read2Byte(REG_PM_GPIO4_OEN))&(~__BIT4)); in HAL_PM_GPIO4_SetPower()
777 HAL_PM_Write2Byte(REG_PM_GPIO4_OUT, (HAL_PM_Read2Byte(REG_PM_GPIO4_OUT))&(~__BIT4)); in HAL_PM_GPIO4_SetPower()
778 HAL_PM_Write2Byte(REG_PM_GPIO4_OEN, (HAL_PM_Read2Byte(REG_PM_GPIO4_OEN))&(~__BIT4)); in HAL_PM_GPIO4_SetPower()
/utopia/UTPA2-700.0.x/modules/pm/hal/mustang/pm/
H A DhalPM.c355 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
592 HAL_PM_WriteByte(0x2e53,HAL_PM_ReadByte(0x2e53)&(~__BIT4)); //8051 reset in HAL_PM_SetSRAMOffsetForMCU()
624 HAL_PM_WriteByte(0x2e53,HAL_PM_ReadByte(0x2e53)|__BIT4); //release 8051 reset in HAL_PM_SetSRAMOffsetForMCU()
639 HAL_PM_WriteByte(0x2e53,HAL_PM_ReadByte(0x2e53)&(~__BIT4)); //8051 reset in HAL_PM_SetDRAMOffsetForMCU()
673 HAL_PM_WriteByte(0x2e53,HAL_PM_ReadByte(0x2e53)|__BIT4); //release 8051 reset in HAL_PM_SetDRAMOffsetForMCU()
744 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
772 HAL_PM_Write2Byte(REG_PM_GPIO4_OUT, (HAL_PM_Read2Byte(REG_PM_GPIO4_OUT))|(__BIT4)); in HAL_PM_GPIO4_SetPower()
773 HAL_PM_Write2Byte(REG_PM_GPIO4_OEN, (HAL_PM_Read2Byte(REG_PM_GPIO4_OEN))&(~__BIT4)); in HAL_PM_GPIO4_SetPower()
777 HAL_PM_Write2Byte(REG_PM_GPIO4_OUT, (HAL_PM_Read2Byte(REG_PM_GPIO4_OUT))&(~__BIT4)); in HAL_PM_GPIO4_SetPower()
778 HAL_PM_Write2Byte(REG_PM_GPIO4_OEN, (HAL_PM_Read2Byte(REG_PM_GPIO4_OEN))&(~__BIT4)); in HAL_PM_GPIO4_SetPower()
/utopia/UTPA2-700.0.x/modules/bdma/hal/k6lite/bdma/
H A DhalBDMA.c422 … HAL_BDMA_WriteByte(0x0e53UL, HAL_BDMA_ReadByte(0x0e53UL) | __BIT4); //release 8051 reset in __pm51ctl()
425 HAL_BDMA_WriteByte(0x0e53,HAL_BDMA_ReadByte(0x0e53) & (~__BIT4)); //8051 reset in __pm51ctl()
464 … HAL_BDMA_WriteByte(0x0e53UL,HAL_BDMA_ReadByte(0x0e53UL)|__BIT4); //release 8051 reset in __pm51ctl()
467 HAL_BDMA_WriteByte(0x0e53,HAL_BDMA_ReadByte(0x0e53)&(~__BIT4)); //8051 reset in __pm51ctl()
484 HAL_BDMA_WriteByte(0x0e53UL,HAL_BDMA_ReadByte(0x0e53UL)|__BIT4); //release 8051 reset in __pm51ctl()
487 HAL_BDMA_WriteByte(0x0e53,HAL_BDMA_ReadByte(0x0e53)&(~__BIT4)); //8051 reset in __pm51ctl()
1008 HAL_BDMA_WriteByte(0x0e41,HAL_BDMA_ReadByte(0x0e41)&(~__BIT4)); in HAL_BDMA_SetSPIOffsetForMCU()
1012 HAL_BDMA_WriteByte(0x0e40,HAL_BDMA_ReadByte(0x0e40)|(__BIT4)); in HAL_BDMA_SetSPIOffsetForMCU()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mainz/hwi2c/
H A DregHWI2C.h122 #define CHIP_MIIC1_PAD_1 (__BIT4)
123 #define CHIP_MIIC1_PAD_MSK (__BIT4)
148 #define _MIIC_CFG_EN_TMTINT (__BIT4)
166 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
172 #define _INT_CLKSTR (__BIT4)
190 #define _DMA_CFG_MIUPRI (__BIT4)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mustang/hwi2c/
H A DregHWI2C.h129 #define CHIP_MIIC2_PAD_1 (__BIT4)
131 #define CHIP_MIIC2_PAD_MSK (__BIT4|__BIT5)
168 #define _MIIC_CFG_EN_TMTINT (__BIT4)
186 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
192 #define _INT_CLKSTR (__BIT4)
210 #define _DMA_CFG_MIUPRI (__BIT4)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maldives/hwi2c/
H A DregHWI2C.h129 #define CHIP_MIIC2_PAD_1 (__BIT4)
131 #define CHIP_MIIC2_PAD_MSK (__BIT4|__BIT5)
168 #define _MIIC_CFG_EN_TMTINT (__BIT4)
186 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
192 #define _INT_CLKSTR (__BIT4)
210 #define _DMA_CFG_MIUPRI (__BIT4)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/manhattan/hwi2c/
H A DregHWI2C.h170 #define _MIIC_CFG_EN_TMTINT (__BIT4)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
194 #define _INT_CLKSTR (__BIT4)
211 #define _ADV_START2B_DELAY (__BIT4)
230 #define _DMA_CFG_MIUPRI (__BIT4)
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7821/hwi2c/
H A DregHWI2C.h170 #define _MIIC_CFG_EN_TMTINT (__BIT4)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
194 #define _INT_CLKSTR (__BIT4)
211 #define _ADV_START2B_DELAY (__BIT4)
230 #define _DMA_CFG_MIUPRI (__BIT4)
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maserati/hwi2c/
H A DregHWI2C.h170 #define _MIIC_CFG_EN_TMTINT (__BIT4)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
194 #define _INT_CLKSTR (__BIT4)
211 #define _ADV_START2B_DELAY (__BIT4)
230 #define _DMA_CFG_MIUPRI (__BIT4)
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7621/hwi2c/
H A DregHWI2C.h170 #define _MIIC_CFG_EN_TMTINT (__BIT4)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
194 #define _INT_CLKSTR (__BIT4)
211 #define _ADV_START2B_DELAY (__BIT4)
230 #define _DMA_CFG_MIUPRI (__BIT4)
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maxim/hwi2c/
H A DregHWI2C.h170 #define _MIIC_CFG_EN_TMTINT (__BIT4)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
194 #define _INT_CLKSTR (__BIT4)
211 #define _ADV_START2B_DELAY (__BIT4)
230 #define _DMA_CFG_MIUPRI (__BIT4)
263 #define _DMA_RESERV_CTL (__BIT4 |__BIT5 |__BIT6 |__BIT7)
/utopia/UTPA2-700.0.x/modules/pm/hal/mainz/pm/
H A DhalPM.c356 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
593 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetSRAMOffsetForMCU()
625 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetSRAMOffsetForMCU()
641 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetDRAMOffsetForMCU()
674 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetDRAMOffsetForMCU()
735 HAL_PM_WriteRegBit(0x002e53UL, DISABLE, __BIT4); //8051 reset disable in HAL_PM_Disable51()
755 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/k6lite/pm/
H A DhalPM.c412 … HAL_PM_WriteByte(0x0e53UL,HAL_PM_ReadByte(0x0e53UL)|__BIT4); //release 8051 reset in __pm51ctl()
415 HAL_PM_WriteByte(0x0e53,HAL_PM_ReadByte(0x0e53)&(~__BIT4)); //8051 reset in __pm51ctl()
453 … HAL_PM_WriteByte(0x0e53UL,HAL_PM_ReadByte(0x0e53UL)|__BIT4); //release 8051 reset in __pm51ctl()
456 HAL_PM_WriteByte(0x0e53,HAL_PM_ReadByte(0x0e53)&(~__BIT4)); //8051 reset in __pm51ctl()
473 HAL_PM_WriteByte(0x0e53UL,HAL_PM_ReadByte(0x0e53UL)|__BIT4); //release 8051 reset in __pm51ctl()
476 HAL_PM_WriteByte(0x0e53,HAL_PM_ReadByte(0x0e53)&(~__BIT4)); //8051 reset in __pm51ctl()
861 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/maserati/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
591 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetSRAMOffsetForMCU()
623 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetSRAMOffsetForMCU()
639 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetDRAMOffsetForMCU()
672 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetDRAMOffsetForMCU()
733 HAL_PM_WriteRegBit(0x002e53UL, DISABLE, __BIT4); //8051 reset disable in HAL_PM_Disable51()
753 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/manhattan/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
591 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetSRAMOffsetForMCU()
623 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetSRAMOffsetForMCU()
639 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetDRAMOffsetForMCU()
672 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetDRAMOffsetForMCU()
733 HAL_PM_WriteRegBit(0x002e53UL, DISABLE, __BIT4); //8051 reset disable in HAL_PM_Disable51()
753 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/M7621/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
591 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetSRAMOffsetForMCU()
623 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetSRAMOffsetForMCU()
639 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetDRAMOffsetForMCU()
672 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetDRAMOffsetForMCU()
733 HAL_PM_WriteRegBit(0x002e53UL, DISABLE, __BIT4); //8051 reset disable in HAL_PM_Disable51()
753 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/maxim/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
591 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetSRAMOffsetForMCU()
623 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetSRAMOffsetForMCU()
639 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetDRAMOffsetForMCU()
672 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetDRAMOffsetForMCU()
733 HAL_PM_WriteRegBit(0x002e53UL, DISABLE, __BIT4); //8051 reset disable in HAL_PM_Disable51()
753 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/mooney/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
591 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetSRAMOffsetForMCU()
623 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetSRAMOffsetForMCU()
639 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetDRAMOffsetForMCU()
672 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetDRAMOffsetForMCU()
733 HAL_PM_WriteRegBit(0x002e53UL, DISABLE, __BIT4); //8051 reset disable in HAL_PM_Disable51()
753 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/M7821/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
591 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetSRAMOffsetForMCU()
623 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetSRAMOffsetForMCU()
639 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetDRAMOffsetForMCU()
672 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetDRAMOffsetForMCU()
733 HAL_PM_WriteRegBit(0x002e53UL, DISABLE, __BIT4); //8051 reset disable in HAL_PM_Disable51()
753 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/macan/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
593 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetSRAMOffsetForMCU()
625 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetSRAMOffsetForMCU()
641 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT4)); //8051 reset in HAL_PM_SetDRAMOffsetForMCU()
674 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT4); //release 8051 reset in HAL_PM_SetDRAMOffsetForMCU()
735 HAL_PM_WriteRegBit(0x002e53UL, DISABLE, __BIT4); //8051 reset disable in HAL_PM_Disable51()
755 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)
/utopia/UTPA2-700.0.x/modules/pm/hal/k6/pm/
H A DhalPM.c411 … HAL_PM_WriteByte(0x0e53UL,HAL_PM_ReadByte(0x0e53UL)|__BIT4); //release 8051 reset in __pm51ctl()
414 HAL_PM_WriteByte(0x0e53,HAL_PM_ReadByte(0x0e53)&(~__BIT4)); //8051 reset in __pm51ctl()
452 … HAL_PM_WriteByte(0x0e53UL,HAL_PM_ReadByte(0x0e53UL)|__BIT4); //release 8051 reset in __pm51ctl()
455 HAL_PM_WriteByte(0x0e53,HAL_PM_ReadByte(0x0e53)&(~__BIT4)); //8051 reset in __pm51ctl()
472 HAL_PM_WriteByte(0x0e53UL,HAL_PM_ReadByte(0x0e53UL)|__BIT4); //release 8051 reset in __pm51ctl()
475 HAL_PM_WriteByte(0x0e53,HAL_PM_ReadByte(0x0e53)&(~__BIT4)); //8051 reset in __pm51ctl()
860 #define TRIGGER_MASK (__BIT7|__BIT6|__BIT5|__BIT4)

1234