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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6lite/hwi2c/
H A DregHWI2C.h118 #define CHIP_MIIC0_PAD_1 (__BIT0)
120 #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1)
121 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1)
138 #define REG_HWI2C_MIIC_VER_V3 (__BIT1|__BIT0)
139 #define REG_HWI2C_MIIC_VER_MSK (__BIT1|__BIT0)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
169 #define _MIIC_CFG_RESET (__BIT0)
178 #define _CMD_START (__BIT0)
180 #define _CMD_STOP (__BIT0)
183 #define _WDATA_GET_ACKBIT (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/kano/hwi2c/
H A DregHWI2C.h118 #define CHIP_MIIC0_PAD_1 (__BIT0)
120 #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1)
121 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1)
138 #define REG_HWI2C_MIIC_VER_V3 (__BIT1|__BIT0)
139 #define REG_HWI2C_MIIC_VER_MSK (__BIT1|__BIT0)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
169 #define _MIIC_CFG_RESET (__BIT0)
178 #define _CMD_START (__BIT0)
180 #define _CMD_STOP (__BIT0)
183 #define _WDATA_GET_ACKBIT (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6/hwi2c/
H A DregHWI2C.h118 #define CHIP_MIIC0_PAD_1 (__BIT0)
120 #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1)
121 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1)
138 #define REG_HWI2C_MIIC_VER_V3 (__BIT1|__BIT0)
139 #define REG_HWI2C_MIIC_VER_MSK (__BIT1|__BIT0)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
169 #define _MIIC_CFG_RESET (__BIT0)
178 #define _CMD_START (__BIT0)
180 #define _CMD_STOP (__BIT0)
183 #define _WDATA_GET_ACKBIT (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/curry/hwi2c/
H A DregHWI2C.h118 #define CHIP_MIIC0_PAD_1 (__BIT0)
120 #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1)
121 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1)
138 #define REG_HWI2C_MIIC_VER_V3 (__BIT1|__BIT0)
139 #define REG_HWI2C_MIIC_VER_MSK (__BIT1|__BIT0)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
169 #define _MIIC_CFG_RESET (__BIT0)
178 #define _CMD_START (__BIT0)
180 #define _CMD_STOP (__BIT0)
183 #define _WDATA_GET_ACKBIT (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/manhattan/hwi2c/
H A DregHWI2C.h115 #define CHIP_MIIC0_PAD_1 (__BIT0) //PAD_GPIO28/PAD_GPIO29
116 #define CHIP_MIIC0_PAD_MSK (__BIT0)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
144 #define CHIP_MIIC4_PAD_1 (__BIT0) //PAD_GPIO30/PAD_GPIO31
145 #define CHIP_MIIC4_PAD_MSK (__BIT0)
166 #define _MIIC_CFG_RESET (__BIT0)
175 #define _CMD_START (__BIT0)
177 #define _CMD_STOP (__BIT0)
180 #define _WDATA_GET_ACKBIT (__BIT0)
183 #define _RDATA_CFG_TRIG (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7821/hwi2c/
H A DregHWI2C.h115 #define CHIP_MIIC0_PAD_1 (__BIT0) //PAD_GPIO28/PAD_GPIO29
116 #define CHIP_MIIC0_PAD_MSK (__BIT0)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
144 #define CHIP_MIIC4_PAD_1 (__BIT0) //PAD_GPIO30/PAD_GPIO31
145 #define CHIP_MIIC4_PAD_MSK (__BIT0)
166 #define _MIIC_CFG_RESET (__BIT0)
175 #define _CMD_START (__BIT0)
177 #define _CMD_STOP (__BIT0)
180 #define _WDATA_GET_ACKBIT (__BIT0)
183 #define _RDATA_CFG_TRIG (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maserati/hwi2c/
H A DregHWI2C.h115 #define CHIP_MIIC0_PAD_1 (__BIT0) //PAD_GPIO28/PAD_GPIO29
116 #define CHIP_MIIC0_PAD_MSK (__BIT0)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
144 #define CHIP_MIIC4_PAD_1 (__BIT0) //PAD_GPIO30/PAD_GPIO31
145 #define CHIP_MIIC4_PAD_MSK (__BIT0)
166 #define _MIIC_CFG_RESET (__BIT0)
175 #define _CMD_START (__BIT0)
177 #define _CMD_STOP (__BIT0)
180 #define _WDATA_GET_ACKBIT (__BIT0)
183 #define _RDATA_CFG_TRIG (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7621/hwi2c/
H A DregHWI2C.h115 #define CHIP_MIIC0_PAD_1 (__BIT0) //PAD_GPIO28/PAD_GPIO29
116 #define CHIP_MIIC0_PAD_MSK (__BIT0)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
144 #define CHIP_MIIC4_PAD_1 (__BIT0) //PAD_GPIO30/PAD_GPIO31
145 #define CHIP_MIIC4_PAD_MSK (__BIT0)
166 #define _MIIC_CFG_RESET (__BIT0)
175 #define _CMD_START (__BIT0)
177 #define _CMD_STOP (__BIT0)
180 #define _WDATA_GET_ACKBIT (__BIT0)
183 #define _RDATA_CFG_TRIG (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maxim/hwi2c/
H A DregHWI2C.h115 #define CHIP_MIIC0_PAD_1 (__BIT0) //PAD_GPIO28/PAD_GPIO29
116 #define CHIP_MIIC0_PAD_MSK (__BIT0)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
144 #define CHIP_MIIC4_PAD_1 (__BIT0) //PAD_GPIO30/PAD_GPIO31
145 #define CHIP_MIIC4_PAD_MSK (__BIT0)
166 #define _MIIC_CFG_RESET (__BIT0)
175 #define _CMD_START (__BIT0)
177 #define _CMD_STOP (__BIT0)
180 #define _WDATA_GET_ACKBIT (__BIT0)
183 #define _RDATA_CFG_TRIG (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mooney/hwi2c/
H A DregHWI2C.h115 #define CHIP_MIIC0_PAD_1 (__BIT0) //PAD_GPIO28/PAD_GPIO29
116 #define CHIP_MIIC0_PAD_MSK (__BIT0)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
144 #define CHIP_MIIC4_PAD_1 (__BIT0) //PAD_GPIO30/PAD_GPIO31
145 #define CHIP_MIIC4_PAD_MSK (__BIT0)
166 #define _MIIC_CFG_RESET (__BIT0)
175 #define _CMD_START (__BIT0)
177 #define _CMD_STOP (__BIT0)
180 #define _WDATA_GET_ACKBIT (__BIT0)
183 #define _RDATA_CFG_TRIG (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/messi/hwi2c/
H A DregHWI2C.h115 #define CHIP_MIIC0_PAD_1 (__BIT0) //PAD_GPIO28/PAD_GPIO29
116 #define CHIP_MIIC0_PAD_MSK (__BIT0)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
144 #define CHIP_MIIC4_PAD_1 (__BIT0) //PAD_GPIO30/PAD_GPIO31
145 #define CHIP_MIIC4_PAD_MSK (__BIT0)
166 #define _MIIC_CFG_RESET (__BIT0)
175 #define _CMD_START (__BIT0)
177 #define _CMD_STOP (__BIT0)
180 #define _WDATA_GET_ACKBIT (__BIT0)
183 #define _RDATA_CFG_TRIG (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/macan/hwi2c/
H A DregHWI2C.h115 #define CHIP_MIIC0_PAD_1 (__BIT0) //PAD_GPIO28/PAD_GPIO29
116 #define CHIP_MIIC0_PAD_MSK (__BIT0)
134 #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0)
144 #define CHIP_MIIC4_PAD_1 (__BIT0) //PAD_GPIO30/PAD_GPIO31
145 #define CHIP_MIIC4_PAD_MSK (__BIT0)
166 #define _MIIC_CFG_RESET (__BIT0)
175 #define _CMD_START (__BIT0)
177 #define _CMD_STOP (__BIT0)
180 #define _WDATA_GET_ACKBIT (__BIT0)
183 #define _RDATA_CFG_TRIG (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mainz/hwi2c/
H A DregHWI2C.h116 #define CHIP_MIIC0_PAD_1 (__BIT0) //PAD_GPIO28/PAD_GPIO29
117 #define CHIP_MIIC0_PAD_MSK (__BIT0)
127 #define CHIP_MIIC2_PAD_0 (__BIT0)
129 #define CHIP_MIIC2_PAD_MSK (__BIT1|__BIT0)
144 #define _MIIC_CFG_RESET (__BIT0)
153 #define _CMD_START (__BIT0)
155 #define _CMD_STOP (__BIT0)
158 #define _WDATA_GET_ACKBIT (__BIT0)
161 #define _RDATA_CFG_TRIG (__BIT0)
164 #define _INT_CTL (__BIT0) //write this register to clear int
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mustang/hwi2c/
H A DregHWI2C.h115 #define CHIP_MIIC0_PAD_1 (__BIT0)
117 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1)
164 #define _MIIC_CFG_RESET (__BIT0)
173 #define _CMD_START (__BIT0)
175 #define _CMD_STOP (__BIT0)
178 #define _WDATA_GET_ACKBIT (__BIT0)
181 #define _RDATA_CFG_TRIG (__BIT0)
184 #define _INT_CTL (__BIT0) //write this register to clear int
186 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
188 #define _INT_STARTDET (__BIT0)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maldives/hwi2c/
H A DregHWI2C.h115 #define CHIP_MIIC0_PAD_1 (__BIT0)
117 #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1)
164 #define _MIIC_CFG_RESET (__BIT0)
173 #define _CMD_START (__BIT0)
175 #define _CMD_STOP (__BIT0)
178 #define _WDATA_GET_ACKBIT (__BIT0)
181 #define _RDATA_CFG_TRIG (__BIT0)
184 #define _INT_CTL (__BIT0) //write this register to clear int
186 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
188 #define _INT_STARTDET (__BIT0)
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/utopia/UTPA2-700.0.x/modules/pm/hal/mainz/pm/
H A DhalPM.c356 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
541 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
592 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetSRAMOffsetForMCU()
603 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetSRAMOffsetForMCU()
609 HAL_PM_WriteRegBit(0x001018UL, ENABLE , __BIT0); //SRAM enable in HAL_PM_SetSRAMOffsetForMCU()
623 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetSRAMOffsetForMCU()
640 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetDRAMOffsetForMCU()
651 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetDRAMOffsetForMCU()
657 HAL_PM_WriteRegBit(0x001018UL, DISABLE , __BIT0); //SRAM disable in HAL_PM_SetDRAMOffsetForMCU()
672 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetDRAMOffsetForMCU()
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/maserati/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
539 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
590 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetSRAMOffsetForMCU()
601 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetSRAMOffsetForMCU()
607 HAL_PM_WriteRegBit(0x001018UL, ENABLE , __BIT0); //SRAM enable in HAL_PM_SetSRAMOffsetForMCU()
621 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetSRAMOffsetForMCU()
638 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetDRAMOffsetForMCU()
649 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetDRAMOffsetForMCU()
655 HAL_PM_WriteRegBit(0x001018UL, DISABLE , __BIT0); //SRAM disable in HAL_PM_SetDRAMOffsetForMCU()
670 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetDRAMOffsetForMCU()
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/manhattan/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
539 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
590 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetSRAMOffsetForMCU()
601 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetSRAMOffsetForMCU()
607 HAL_PM_WriteRegBit(0x001018UL, ENABLE , __BIT0); //SRAM enable in HAL_PM_SetSRAMOffsetForMCU()
621 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetSRAMOffsetForMCU()
638 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetDRAMOffsetForMCU()
649 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetDRAMOffsetForMCU()
655 HAL_PM_WriteRegBit(0x001018UL, DISABLE , __BIT0); //SRAM disable in HAL_PM_SetDRAMOffsetForMCU()
670 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetDRAMOffsetForMCU()
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/M7621/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
539 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
590 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetSRAMOffsetForMCU()
601 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetSRAMOffsetForMCU()
607 HAL_PM_WriteRegBit(0x001018UL, ENABLE , __BIT0); //SRAM enable in HAL_PM_SetSRAMOffsetForMCU()
621 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetSRAMOffsetForMCU()
638 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetDRAMOffsetForMCU()
649 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetDRAMOffsetForMCU()
655 HAL_PM_WriteRegBit(0x001018UL, DISABLE , __BIT0); //SRAM disable in HAL_PM_SetDRAMOffsetForMCU()
670 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetDRAMOffsetForMCU()
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/maxim/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
539 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
590 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetSRAMOffsetForMCU()
601 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetSRAMOffsetForMCU()
607 HAL_PM_WriteRegBit(0x001018UL, ENABLE , __BIT0); //SRAM enable in HAL_PM_SetSRAMOffsetForMCU()
621 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetSRAMOffsetForMCU()
638 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetDRAMOffsetForMCU()
649 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetDRAMOffsetForMCU()
655 HAL_PM_WriteRegBit(0x001018UL, DISABLE , __BIT0); //SRAM disable in HAL_PM_SetDRAMOffsetForMCU()
670 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetDRAMOffsetForMCU()
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/mooney/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
539 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
590 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetSRAMOffsetForMCU()
601 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetSRAMOffsetForMCU()
607 HAL_PM_WriteRegBit(0x001018UL, ENABLE , __BIT0); //SRAM enable in HAL_PM_SetSRAMOffsetForMCU()
621 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetSRAMOffsetForMCU()
638 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetDRAMOffsetForMCU()
649 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetDRAMOffsetForMCU()
655 HAL_PM_WriteRegBit(0x001018UL, DISABLE , __BIT0); //SRAM disable in HAL_PM_SetDRAMOffsetForMCU()
670 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetDRAMOffsetForMCU()
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/M7821/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
539 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
590 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetSRAMOffsetForMCU()
601 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetSRAMOffsetForMCU()
607 HAL_PM_WriteRegBit(0x001018UL, ENABLE , __BIT0); //SRAM enable in HAL_PM_SetSRAMOffsetForMCU()
621 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetSRAMOffsetForMCU()
638 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetDRAMOffsetForMCU()
649 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetDRAMOffsetForMCU()
655 HAL_PM_WriteRegBit(0x001018UL, DISABLE , __BIT0); //SRAM disable in HAL_PM_SetDRAMOffsetForMCU()
670 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetDRAMOffsetForMCU()
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/macan/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
541 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
592 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetSRAMOffsetForMCU()
603 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetSRAMOffsetForMCU()
609 HAL_PM_WriteRegBit(0x001018UL, ENABLE , __BIT0); //SRAM enable in HAL_PM_SetSRAMOffsetForMCU()
623 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetSRAMOffsetForMCU()
640 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetDRAMOffsetForMCU()
651 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetDRAMOffsetForMCU()
657 HAL_PM_WriteRegBit(0x001018UL, DISABLE , __BIT0); //SRAM disable in HAL_PM_SetDRAMOffsetForMCU()
672 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetDRAMOffsetForMCU()
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/messi/pm/
H A DhalPM.c356 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
541 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
592 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetSRAMOffsetForMCU()
603 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetSRAMOffsetForMCU()
609 HAL_PM_WriteRegBit(0x001018UL, ENABLE , __BIT0); //SRAM enable in HAL_PM_SetSRAMOffsetForMCU()
623 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetSRAMOffsetForMCU()
640 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)&(~__BIT0)); in HAL_PM_SetDRAMOffsetForMCU()
651 HAL_PM_WriteRegBit(0x002ba0UL, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetDRAMOffsetForMCU()
657 HAL_PM_WriteRegBit(0x001018UL, DISABLE , __BIT0); //SRAM disable in HAL_PM_SetDRAMOffsetForMCU()
672 HAL_PM_WriteByte(0x2e53UL,HAL_PM_ReadByte(0x2e53UL)|__BIT0); in HAL_PM_SetDRAMOffsetForMCU()
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/utopia/UTPA2-700.0.x/modules/pm/hal/maldives/pm/
H A DhalPM.c355 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
540 HAL_PM_WriteRegBit(0x002ba0, ENABLE, __BIT0); //disable i cache in HAL_PM_SetSPIOffsetForMCU()
591 HAL_PM_WriteByte(0x2e53,HAL_PM_ReadByte(0x2e53)&(~__BIT0)); in HAL_PM_SetSRAMOffsetForMCU()
602 HAL_PM_WriteRegBit(0x002ba0, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetSRAMOffsetForMCU()
608 HAL_PM_WriteRegBit(0x001018, ENABLE , __BIT0); //SRAM enable in HAL_PM_SetSRAMOffsetForMCU()
622 HAL_PM_WriteByte(0x2e53,HAL_PM_ReadByte(0x2e53)|__BIT0); in HAL_PM_SetSRAMOffsetForMCU()
638 HAL_PM_WriteByte(0x2e53,HAL_PM_ReadByte(0x2e53)&(~__BIT0)); in HAL_PM_SetDRAMOffsetForMCU()
649 HAL_PM_WriteRegBit(0x002ba0, ENABLE , __BIT0); //disable i cache (enable icache bypass) in HAL_PM_SetDRAMOffsetForMCU()
655 HAL_PM_WriteRegBit(0x001018, DISABLE , __BIT0); //SRAM disable in HAL_PM_SetDRAMOffsetForMCU()
671 HAL_PM_WriteByte(0x2e53,HAL_PM_ReadByte(0x2e53)|__BIT0); in HAL_PM_SetDRAMOffsetForMCU()
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