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Searched refs:_RegCtrl3 (Results 1 – 4 of 4) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsp/
H A DhalTSP.c51 static REG_Ctrl3* _RegCtrl3 = NULL; // TSP4 variable
208 _RegCtrl3 = (REG_Ctrl3*)(u32BankAddr + 0xE0600UL); // TSP4 0x1703 in HAL_TSP_SetBank()
336 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
368 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PUSI_3BYTE_MODE); //Enable audio 3 byte mode in HAL_TSP_HwPatch()
374 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BLK_AD_SCMBTIS_TSP); in HAL_TSP_HwPatch()
389 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_FIX_192_TIMER_0_EN); in HAL_TSP_HwPatch()
392 REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW); in HAL_TSP_HwPatch()
408 …REG16_SET(&_RegCtrl3->CFG3_18, CFG3_18_HD_0000_TO_SECTION_RVU | CFG3_18_HD_0000_TO_SECTION_DIRECTV… in HAL_TSP_HwPatch()
653 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_Power()
656 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP in HAL_TSP_Power()
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/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/tsp/
H A DhalTSP.c55 static REG_Ctrl3* _RegCtrl3 = NULL; variable
211 _RegCtrl3 = (REG_Ctrl3*)(u32BankAddr + 0xE0600UL); //TSP4 0x1703 in HAL_TSP_SetBank()
338 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
370 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PUSI_3BYTE_MODE); //Enable audio 3 byte mode in HAL_TSP_HwPatch()
376 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BLK_AD_SCMBTIS_TSP); in HAL_TSP_HwPatch()
383 REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW); in HAL_TSP_HwPatch()
395 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_FIX_192_TIMER_0_EN); in HAL_TSP_HwPatch()
635 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_Power()
638 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP in HAL_TSP_Power()
643 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP in HAL_TSP_Power()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsp/
H A DhalTSP.c47 static REG_Ctrl3* _RegCtrl3 = NULL; // TSP4 variable
190 _RegCtrl3 = (REG_Ctrl3*)(u32BankAddr + 0xE0600UL); // TSP4 0x1703 in HAL_TSP_SetBank()
259 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
291 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PUSI_3BYTE_MODE); //Enable audio 3 byte mode in HAL_TSP_HwPatch()
297 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BLK_AD_SCMBTIS_TSP); in HAL_TSP_HwPatch()
312 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_FIX_192_TIMER_0_EN); in HAL_TSP_HwPatch()
315 REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW); in HAL_TSP_HwPatch()
559 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_Power()
562 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP in HAL_TSP_Power()
567 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP in HAL_TSP_Power()
[all …]
/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/tsp/
H A DhalTSP.c42 static REG_Ctrl3* _RegCtrl3 = NULL; variable
183 _RegCtrl3 = (REG_Ctrl3*)(u32BankAddr + 0xE0600UL); //TSP4 0x1703 in HAL_TSP_SetBank()
251 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_HwPatch()
276 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PUSI_3BYTE_MODE); //Enable audio 3 byte mode in HAL_TSP_HwPatch()
280 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BLK_AD_SCMBTIS_TSP); in HAL_TSP_HwPatch()
287 REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW); in HAL_TSP_HwPatch()
293 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_FIX_192_TIMER_0_EN); in HAL_TSP_HwPatch()
441 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE); //TSP in HAL_TSP_Power()
442 …REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_MMFI1_REQ_MCM_DISABLE); // disable MMFI1 MCM, and never ena… in HAL_TSP_Power()
477 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION); in HAL_TSP_Power()
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