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Searched refs:VPU_REG_HI_MBOX_SET (Results 1 – 25 of 68) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/vpu/
H A DhalVPU.c539 … _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX0_SET , VPU_REG_HI_MBOX0_SET ); in HAL_VPU_MBoxSend()
543 … _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX1_SET , VPU_REG_HI_MBOX1_SET ); in HAL_VPU_MBoxSend()
H A DregVPU.h299 #define VPU_REG_HI_MBOX_SET ( REG_MBX_BASE+(0x005f<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/vpu/
H A DhalVPU.c539 … _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX0_SET , VPU_REG_HI_MBOX0_SET ); in HAL_VPU_MBoxSend()
543 … _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX1_SET , VPU_REG_HI_MBOX1_SET ); in HAL_VPU_MBoxSend()
H A DregVPU.h299 #define VPU_REG_HI_MBOX_SET ( REG_MBX_BASE+(0x005f<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/vpu/
H A DhalVPU.c539 … _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX0_SET , VPU_REG_HI_MBOX0_SET ); in HAL_VPU_MBoxSend()
543 … _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX1_SET , VPU_REG_HI_MBOX1_SET ); in HAL_VPU_MBoxSend()
H A DregVPU.h299 #define VPU_REG_HI_MBOX_SET ( REG_MBX_BASE+(0x005f<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/vpu/
H A DhalVPU.c539 … _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX0_SET , VPU_REG_HI_MBOX0_SET ); in HAL_VPU_MBoxSend()
543 … _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX1_SET , VPU_REG_HI_MBOX1_SET ); in HAL_VPU_MBoxSend()
H A DregVPU.h299 #define VPU_REG_HI_MBOX_SET ( REG_MBX_BASE+(0x005f<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/vpu/
H A DhalVPU.c539 … _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX0_SET , VPU_REG_HI_MBOX0_SET ); in HAL_VPU_MBoxSend()
543 … _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX1_SET , VPU_REG_HI_MBOX1_SET ); in HAL_VPU_MBoxSend()
H A DregVPU.h299 #define VPU_REG_HI_MBOX_SET ( REG_MBX_BASE+(0x005f<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/vpu/
H A DhalVPU.c539 … _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX0_SET , VPU_REG_HI_MBOX0_SET ); in HAL_VPU_MBoxSend()
543 … _VPU_WriteWordMask( VPU_REG_HI_MBOX_SET , VPU_REG_HI_MBOX1_SET , VPU_REG_HI_MBOX1_SET ); in HAL_VPU_MBoxSend()
H A DregVPU.h299 #define VPU_REG_HI_MBOX_SET ( REG_MBX_BASE+(0x005f<<1)) macro
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v1/hal/manhattan/jpd/
H A DhalJPD.c1516 __HAL_JPD_WriteBit(VPU_REG_HI_MBOX_SET, TRUE, VPU_REG_HI_MBOX0_SET); in HAL_JPD_SendVPUMBox()
1520 __HAL_JPD_WriteBit(VPU_REG_HI_MBOX_SET, TRUE, VPU_REG_HI_MBOX1_SET); in HAL_JPD_SendVPUMBox()
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v1/hal/M7621/jpd/
H A DhalJPD.c1516 __HAL_JPD_WriteBit(VPU_REG_HI_MBOX_SET, TRUE, VPU_REG_HI_MBOX0_SET); in HAL_JPD_SendVPUMBox()
1520 __HAL_JPD_WriteBit(VPU_REG_HI_MBOX_SET, TRUE, VPU_REG_HI_MBOX1_SET); in HAL_JPD_SendVPUMBox()
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v1/hal/M7821/jpd/
H A DhalJPD.c1516 __HAL_JPD_WriteBit(VPU_REG_HI_MBOX_SET, TRUE, VPU_REG_HI_MBOX0_SET); in HAL_JPD_SendVPUMBox()
1520 __HAL_JPD_WriteBit(VPU_REG_HI_MBOX_SET, TRUE, VPU_REG_HI_MBOX1_SET); in HAL_JPD_SendVPUMBox()
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v1/hal/maxim/jpd/
H A DhalJPD.c1516 __HAL_JPD_WriteBit(VPU_REG_HI_MBOX_SET, TRUE, VPU_REG_HI_MBOX0_SET); in HAL_JPD_SendVPUMBox()
1520 __HAL_JPD_WriteBit(VPU_REG_HI_MBOX_SET, TRUE, VPU_REG_HI_MBOX1_SET); in HAL_JPD_SendVPUMBox()
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v1/hal/macan/jpd/
H A DhalJPD.c1516 __HAL_JPD_WriteBit(VPU_REG_HI_MBOX_SET, TRUE, VPU_REG_HI_MBOX0_SET); in HAL_JPD_SendVPUMBox()
1520 __HAL_JPD_WriteBit(VPU_REG_HI_MBOX_SET, TRUE, VPU_REG_HI_MBOX1_SET); in HAL_JPD_SendVPUMBox()
/utopia/UTPA2-700.0.x/modules/ojpd_vdec_v1/hal/maserati/jpd/
H A DhalJPD.c1516 __HAL_JPD_WriteBit(VPU_REG_HI_MBOX_SET, TRUE, VPU_REG_HI_MBOX0_SET); in HAL_JPD_SendVPUMBox()
1520 __HAL_JPD_WriteBit(VPU_REG_HI_MBOX_SET, TRUE, VPU_REG_HI_MBOX1_SET); in HAL_JPD_SendVPUMBox()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/vpu_ex/
H A DregVPU_EX.h302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/vpu_ex/
H A DregVPU_EX.h302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/vpu_ex/
H A DregVPU_EX.h302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/vpu_ex/
H A DregVPU_EX.h302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/vpu_ex/
H A DregVPU_EX.h302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/vpu_ex/
H A DregVPU_EX.h302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/vpu_ex/
H A DregVPU_EX.h302 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1)) macro

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