Home
last modified time | relevance | path

Searched refs:UART_FCR (Results 1 – 25 of 48) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/uart/hal/mustang/uart/
H A DhalUART.c986 …AEON_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_Aeon_Open()
1183 u8RegData = UART_REG8(UART_FCR) | 0x07; in HAL_UART_PIU_Set_Baudrate()
1190 UART_REG8(UART_FCR) = u8RegData; in HAL_UART_PIU_Set_Baudrate()
1519 …UART_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_PIU_Open()
H A DregUART.h182 #define UART_FCR 2 // Out: FIFO Control Register macro
196 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/maldives/uart/
H A DhalUART.c986 …AEON_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_Aeon_Open()
1183 u8RegData = UART_REG8(UART_FCR) | 0x07; in HAL_UART_PIU_Set_Baudrate()
1190 UART_REG8(UART_FCR) = u8RegData; in HAL_UART_PIU_Set_Baudrate()
1519 …UART_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_PIU_Open()
H A DregUART.h177 #define UART_FCR 2 // Out: FIFO Control Register macro
191 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/macan/uart/
H A DhalUART.c1015 …AEON_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_Aeon_Open()
1205 u8RegData = UART_REG8(UART_FCR) | 0x07; in HAL_UART_PIU_Set_Baudrate()
1210 UART_REG8(UART_FCR) = u8RegData; in HAL_UART_PIU_Set_Baudrate()
1580 …UART_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_PIU_Open()
H A DregUART.h197 #define UART_FCR 2 // Out: FIFO Control Register macro
211 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/messi/uart/
H A DhalUART.c1014 …AEON_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_Aeon_Open()
1204 u8RegData = UART_REG8(UART_FCR) | 0x07; in HAL_UART_PIU_Set_Baudrate()
1209 UART_REG8(UART_FCR) = u8RegData; in HAL_UART_PIU_Set_Baudrate()
1580 …UART_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_PIU_Open()
H A DregUART.h175 #define UART_FCR 2 // Out: FIFO Control Register macro
189 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/M7621/uart/
H A DhalUART.c1018 …AEON_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_Aeon_Open()
1259 u8RegData = UART_REG8(UART_FCR) | 0x07; in HAL_UART_PIU_Set_Baudrate()
1264 UART_REG8(UART_FCR) = u8RegData; in HAL_UART_PIU_Set_Baudrate()
1677 …UART_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_PIU_Open()
H A DregUART.h213 #define UART_FCR 2 // Out: FIFO Control Register macro
227 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/maserati/uart/
H A DhalUART.c1018 …AEON_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_Aeon_Open()
1259 u8RegData = UART_REG8(UART_FCR) | 0x07; in HAL_UART_PIU_Set_Baudrate()
1264 UART_REG8(UART_FCR) = u8RegData; in HAL_UART_PIU_Set_Baudrate()
1677 …UART_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_PIU_Open()
H A DregUART.h213 #define UART_FCR 2 // Out: FIFO Control Register macro
227 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/maxim/uart/
H A DhalUART.c1018 …AEON_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_Aeon_Open()
1259 u8RegData = UART_REG8(UART_FCR) | 0x07; in HAL_UART_PIU_Set_Baudrate()
1264 UART_REG8(UART_FCR) = u8RegData; in HAL_UART_PIU_Set_Baudrate()
1677 …UART_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_PIU_Open()
H A DregUART.h213 #define UART_FCR 2 // Out: FIFO Control Register macro
227 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/manhattan/uart/
H A DhalUART.c1017 …AEON_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_Aeon_Open()
1258 u8RegData = UART_REG8(UART_FCR) | 0x07; in HAL_UART_PIU_Set_Baudrate()
1263 UART_REG8(UART_FCR) = u8RegData; in HAL_UART_PIU_Set_Baudrate()
1632 …UART_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_PIU_Open()
H A DregUART.h213 #define UART_FCR 2 // Out: FIFO Control Register macro
227 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/M7821/uart/
H A DhalUART.c1018 …AEON_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_Aeon_Open()
1259 u8RegData = UART_REG8(UART_FCR) | 0x07; in HAL_UART_PIU_Set_Baudrate()
1264 UART_REG8(UART_FCR) = u8RegData; in HAL_UART_PIU_Set_Baudrate()
1680 …UART_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_PIU_Open()
H A DregUART.h217 #define UART_FCR 2 // Out: FIFO Control Register macro
231 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/mainz/uart/
H A DhalUART.c1060 …AEON_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_Aeon_Open()
1250 u8RegData = UART_REG8(UART_FCR) | 0x07; in HAL_UART_PIU_Set_Baudrate()
1255 UART_REG8(UART_FCR) = u8RegData; in HAL_UART_PIU_Set_Baudrate()
1626 …UART_REG8(UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_… in HAL_UART_PIU_Open()
H A DregUART.h175 #define UART_FCR 2 // Out: FIFO Control Register macro
189 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/kano/uart/
H A DregUART.h176 #define UART_FCR 2 // Out: FIFO Control Register macro
190 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/curry/uart/
H A DregUART.h176 #define UART_FCR 2 // Out: FIFO Control Register macro
190 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/mooney/uart/
H A DregUART.h175 #define UART_FCR 2 // Out: FIFO Control Register macro
189 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/k6lite/uart/
H A DregUART.h176 #define UART_FCR 2 // Out: FIFO Control Register macro
190 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/k6/uart/
H A DregUART.h197 #define UART_FCR 2 // Out: FIFO Control Register macro
211 #define UART_FCR (2 * 2) // Out: FIFO Control Register macro

12