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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regUART.h 98 // Description: UART Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_UART_H_ 103 #define _REG_UART_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Global Definition 107 //-------------------------------------------------------------------------------------------------- 108 109 //-------------------------------------------------------------------------------------------------- 110 // Compliation Option 111 //-------------------------------------------------------------------------------------------------- 112 113 //------------------------------------------------------------------------------------------------- 114 // Hardware Capability 115 //------------------------------------------------------------------------------------------------- 116 #if defined(MCU_AEON) 117 #define PIU_UART_VER 1 118 #endif 119 120 #if defined(MCU_MIPS_4KE) 121 #define PIU_UART_VER 2 122 #endif 123 124 #if defined(MCU_MIPS_34K) 125 #define PIU_UART_VER 2 126 #endif 127 128 #if defined(MCU_MIPS_74K) 129 #define PIU_UART_VER 2 130 #endif 131 132 #if defined(MCU_ARM_CA53) 133 #define PIU_UART_VER 2 134 #endif 135 136 #ifndef PIU_UART_VER 137 #define PIU_UART_VER 2 138 #endif 139 140 #define UART_AEON_NUM 3 141 #define UART_PIU_NUM 3 142 143 #define UART_AEON_ADDR 0x90000000 144 #define UART_AEON_IRQ E_INT_IRQ_UART0 145 146 #define UART0_PIU_ADDR 0x1300 147 #define UART0_PIU_IRQ E_INT_IRQ_UART0 148 149 #define UART1_PIU_ADDR 0x20C00 150 #define UART1_PIU_IRQ E_INT_IRQ_UART1 151 152 #define UART2_PIU_ADDR 0x20C80 153 #define UART2_PIU_IRQ E_INT_IRQ_UART2 154 155 #define FUART_PIU_ADDR 0x20D00 156 #define FUART_PIU_IRQ E_INT_IRQ_UART2MCU 157 158 #if defined(MCU_AEON) 159 #define UART_CLK_FREQ 172800000 160 #endif 161 162 #if defined(MCU_MIPS_4KE) 163 #define UART_CLK_FREQ 123000000//123000000 164 #endif 165 166 #if defined(MCU_MIPS_34K) 167 #define UART_CLK_FREQ 123000000//123000000 168 #endif 169 170 #if defined(MCU_MIPS_74K) 171 #define UART_CLK_FREQ 123000000//123000000 172 #endif 173 174 #if defined(MCU_ARM_CA53) 175 #define UART_CLK_FREQ 123000000//123000000 176 #endif 177 178 #ifndef UART_CLK_FREQ 179 #define UART_CLK_FREQ 123000000//123000000 180 #endif 181 182 #ifndef UART_CLK_FREQ_172M 183 #define UART_CLK_FREQ_172M 172000000//172000000 184 #endif 185 186 #ifndef UART_CLK_FREQ_160M 187 #define UART_CLK_FREQ_160M 160000000//160000000 188 #endif 189 190 #ifndef UART_CLK_FREQ_144M 191 #define UART_CLK_FREQ_144M 144000000//144000000 192 #endif 193 194 #ifndef UART_CLK_FREQ_108M 195 #define UART_CLK_FREQ_108M 108000000//108000000 196 #endif 197 198 //------------------------------------------------------------------------------------------------- 199 // Type and Structure 200 //------------------------------------------------------------------------------------------------- 201 202 // 203 // UART Register List 204 // 205 206 #if (PIU_UART_VER == 1) 207 #define UART_RX 0 // In: Receive buffer (DLAB=0) 208 #define UART_TX 0 // Out: Transmit buffer (DLAB=0) 209 #define UART_DLL 0 // Out: Divisor Latch Low (DLAB=1) 210 #define UART_DLM 1 // Out: Divisor Latch High (DLAB=1) 211 #define UART_IER 1 // Out: Interrupt Enable Register 212 #define UART_IIR 2 // In: Interrupt ID Register 213 #define UART_FCR 2 // Out: FIFO Control Register 214 #define UART_LCR 3 // Out: Line Control Register 215 #define UART_MCR 4 // Out: Modem Control Register 216 #define UART_LSR 5 // In: Line Status Register 217 #define UART_USR 7 218 #endif 219 220 #if (PIU_UART_VER == 2) 221 #define UART_RX (0 * 2) // In: Receive buffer (DLAB=0) 222 #define UART_TX (0 * 2) // Out: Transmit buffer (DLAB=0) 223 #define UART_DLL (0 * 2) // Out: Divisor Latch Low (DLAB=1) 224 #define UART_DLM (1 * 2) // Out: Divisor Latch High (DLAB=1) 225 #define UART_IER (1 * 2) // Out: Interrupt Enable Register 226 #define UART_IIR (2 * 2) // In: Interrupt ID Register 227 #define UART_FCR (2 * 2) // Out: FIFO Control Register 228 #define UART_LCR (3 * 2) // Out: Line Control Register 229 #define UART_MCR (4 * 2) // Out: Modem Control Register 230 #define UART_LSR (5 * 2) // In: Line Status Register 231 #define UART_MSR (6 * 2) // In: Modem Status Register 232 #define UART_USR (7 * 2) // Out: USER Status Register 233 #endif 234 235 #define UART_FIFO 1 // Divisor Latch Low 236 #define UART_EFR 2 // I/O: Extended Features Register 237 #define UART_RB 3 // optional: set rf_pop delay for memack ; [3:0] rf_pop_delay; [6] rf_pop_mode_sel ; [7] reg_rb_read_ack 238 // (DLAB=1, 16C660 only) 239 #define UART_SCR 7 // I/O: Scratch Register 240 #define UART_SCCR 8 // Smartcard Control Register 241 #define UART_SCSR 9 // Smartcard Status Register 242 #define UART_SCFC 10 // Smartcard Fifo Count Register 243 #define UART_SCFI 11 // Smartcard Fifo Index Register 244 #define UART_SCFR 12 // Smartcard Fifo Read Delay Register 245 #define UART_SCMR 13 // Smartcard Mode Register 246 #define UART_DL 0 // Divisor Latch 247 #define UART_DL1_LSB 0 // Divisor Latch Low 248 #define UART_DL2_MSB 0 // Divisor Latch High 249 250 // 251 // UART_FCR(2) 252 // FIFO Control Register (16650 only) 253 // 254 #define UART_FCR_ENABLE_FIFO 0x01 // Enable the FIFO 255 #define UART_FCR_CLEAR_RCVR 0x02 // Clear the RCVR FIFO 256 #define UART_FCR_CLEAR_XMIT 0x04 // Clear the XMIT FIFO 257 #define UART_FCR_DMA_SELECT 0x08 // For DMA applications 258 #define UART_FCR_TRIGGER_MASK 0xC0 // Mask for the FIFO trigger range 259 //#define UART_FCR_TRIGGER_1 0x00 // Mask for trigger set at 1 260 //#define UART_FCR_TRIGGER_4 0x40 // Mask for trigger set at 4 261 #define UART_FCR_TRIGGER_8 0x80 // Mask for trigger set at 8 262 #define UART_FCR_TRIGGER_14 0xC0 // Mask for trigger set at 14 263 264 // 265 // UART_LCR(3) 266 // Line Control Register 267 // Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 268 // UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 269 // 270 #define UART_LCR_WLEN5 0x00 // Wordlength: 5 bits 271 #define UART_LCR_WLEN6 0x01 // Wordlength: 6 bits 272 #define UART_LCR_WLEN7 0x02 // Wordlength: 7 bits 273 #define UART_LCR_WLEN8 0x03 // Wordlength: 8 bits 274 #define UART_LCR_STOP1 0x00 // Stop bits: 0=1 stop bit, 1= 2 stop bits 275 #define UART_LCR_STOP2 0x04 // Stop bits: 0=1 stop bit, 1= 2 stop bits 276 #define UART_LCR_PARITY 0x08 // Parity Enable 277 #define UART_LCR_EPAR 0x10 // Even parity select 278 #define UART_LCR_SPAR 0x20 // Stick parity (?) 279 #define UART_LCR_SBC 0x40 // Set break control 280 #define UART_LCR_DLAB 0x80 // Divisor latch access bit 281 282 // UART_FCR(4) 283 // FIFO Control Register (16650 only) 284 #define UART_FCR_MASK 0x00FF 285 #define UART_FCR_RXFIFO_CLR 0x0001 286 #define UART_FCR_TXFIFO_CLR 0x0002 287 #define UART_FCR_TRIGGER_0 0x0000 288 #define UART_FCR_TRIGGER_1 0x0010 289 #define UART_FCR_TRIGGER_2 0x0020 290 #define UART_FCR_TRIGGER_3 0x0030 291 #define UART_FCR_TRIGGER_4 0x0040 292 #define UART_FCR_TRIGGER_5 0x0050 293 #define UART_FCR_TRIGGER_6 0x0060 294 #define UART_FCR_TRIGGER_7 0x0070 295 296 // 297 // UART_LSR(5) 298 // Line Status Register 299 // 300 #define UART_LSR_DR 0x01 // Receiver data ready 301 #define UART_LSR_OE 0x02 // Overrun error indicator 302 #define UART_LSR_PE 0x04 // Parity error indicator 303 #define UART_LSR_FE 0x08 // Frame error indicator 304 #define UART_LSR_BI 0x10 // Break interrupt indicator 305 #define UART_LSR_THRE 0x20 // Transmit-hold-register empty 306 #define UART_LSR_TEMT 0x40 // Transmitter empty 307 308 // UART_LSR(6) 309 // Line Status Register 310 #define UART_LSR_TXFIFO_FULL 0x0080 // 311 312 // 313 // UART_IIR(2) 314 // Interrupt Identification Register 315 // 316 317 #define UART_IIR_MSI 0x00 // Modem status interrupt 318 #define UART_IIR_NO_INT 0x01 // No interrupts pending 319 #define UART_IIR_THRI 0x02 // Transmitter holding register empty 320 #define UART_IIR_TOI 0x0c // Receive time out interrupt 321 #define UART_IIR_RDI 0x04 // Receiver data interrupt 322 #define UART_IIR_RLSI 0x06 // Receiver line status interrupt 323 #define UART_IIR_ID 0x06 // Mask for the interrupt ID 324 325 // 326 // UART_IER(1) 327 // Interrupt Enable Register 328 // 329 #define UART_IER_RDI 0x01 // Enable receiver data available interrupt 330 #define UART_IER_THRI 0x02 // Enable Transmitter holding reg empty int 331 #define UART_IER_RLSI 0x04 // Enable receiver line status interrupt 332 #define UART_IER_MSI 0x08 // Enable Modem status interrupt 333 334 // UART_IER(3) 335 // Interrupt Enable Register 336 #define UART_IER_MASK 0xFF00 337 #define UART_IER_RDA 0x0100 // Enable receiver data available interrupt 338 #define UART_IER_THRE 0x0200 // Enable Transmitter holding reg empty int 339 340 // 341 // UART_MCR(4) 342 // Modem Control Register 343 // 344 #define UART_MCR_DTR 0x01 // DTR complement 345 #define UART_MCR_RTS 0x02 // RTS complement 346 #define UART_MCR_OUT1 0x04 // Out1 complement 347 #define UART_MCR_OUT2 0x08 // Out2 complement 348 #define UART_MCR_LOOP 0x10 // Enable loopback test mode 349 350 #define UART_MCR_FAST 0x20 // Slow / Fast baud rate mode 351 352 // UART_LCR(5) //2008/07/09 Nick 353 #define UART_LCR_MASK 0xFF00 354 #define UART_LCR_CHAR_BITS_5 0x0000 // Wordlength: 5 bits 355 #define UART_LCR_CHAR_BITS_6 0x0100 // Wordlength: 6 bits 356 #define UART_LCR_CHAR_BITS_7 0x0200 // Wordlength: 7 bits 357 #define UART_LCR_CHAR_BITS_8 0x0300 // Wordlength: 8 bits 358 #define UART_LCR_STOP_BITS_1 0x0000 // 1 bit 359 #define UART_LCR_STOP_BITS_2 0x0400 // 1.5, 2 bit 360 #define UART_LCR_PARITY_EN 0x0800 // Parity Enable 361 #define UART_LCR_EVEN_PARITY_SEL 0x1000 // Even parity select 362 #define UART_LCR_DIVISOR_EN 0x8000 // Divisor latch access bit 363 364 // 365 // UART_MSR(6) 366 // Modem Status Register 367 // 368 #define UART_MSR_ANY_DELTA 0x0F // Any of the delta bits! 369 #define UART_MSR_DCTS 0x01 // Delta CTS 370 #define UART_MSR_DDSR 0x02 // Delta DSR 371 #define UART_MSR_TERI 0x04 // Trailing edge ring indicator 372 #define UART_MSR_DDCD 0x08 // Delta DCD 373 #define UART_MSR_CTS 0x10 // Clear to Send 374 #define UART_MSR_DSR 0x20 // Data Set Ready 375 #define UART_MSR_RI 0x40 // Ring Indicator 376 #define UART_MSR_DCD 0x80 // Data Carrier Detect 377 378 // 379 // UART_EFR(2, UART_LCR_DLAB) 380 // These are the definitions for the Extended Features Register 381 // (StarTech 16C660 only, when DLAB=1) 382 // 383 #define UART_EFR_ENI 0x10 // Enhanced Interrupt 384 #define UART_EFR_SCD 0x20 // Special character detect 385 #define UART_EFR_RTS 0x40 // RTS flow control 386 #define UART_EFR_CTS 0x80 // CTS flow control 387 388 // 389 // UART_SCCR(8) 390 // SmartCard Control Register 391 // 392 #define UART_SCCR_MASK_CARDIN 0x01 // Smartcard card in interrupt mask 393 #define UART_SCCR_MASK_CARDOUT 0x02 // Smartcard card out interrupt mask 394 #define UART_SCCR_TX_BINV 0x04 // Smartcard Tx bit invert 395 #define UART_SCCR_TX_BSWAP 0x08 // Smartcard Tx bit swap 396 #define UART_SCCR_RST 0x10 // Smartcard reset 0->1, UART Rx enable 1 397 #define UART_SCCR_RX_BINV 0x20 // Smartcard Rx bit inverse 398 #define UART_SCCR_RX_BSWAP 0x40 // Smartcard Rx bit swap 399 400 // 401 // UART_SCSR(9) 402 // Smartcard Status Register 403 // 404 #define UART_SCSR_CLK 0x01 // Smartcard clock out 405 #define UART_SCSR_INT_CARDIN 0x02 // Smartcard card in interrupt 406 #define UART_SCSR_INT_CARDOUT 0x04 // Smartcard card out interrupt 407 #define UART_SCSR_DETECT 0x08 // Smartcard detection status 408 409 // 410 // UART_SCFC(10), UART_SCFI(11), UART_SCFR(12) 411 // Smartcard Fifo Register 412 // 413 #define UART_SCFC_MASK 0x07 414 #define UART_SCFI_MASK 0x0F 415 #define UART_SCFR_MASK 0x07 416 417 418 // 419 // UART_SCFR(12) 420 // Smartcard Fifo Read Delay Register 421 #define UART_SCFR_DELAY_MASK 0x03 422 #define UART_SCFR_V_HIGH 0x04 423 #define UART_SCFR_V_ENABLE 0x08 // Vcc = (Vcc_high ^ (Vcc_en & UART_SCSR_INT_CARDOUT)) 424 425 // 426 // UART_SCMR(13) 427 // SMart Mode Register 428 // 429 #define UART_SCMR_RETRY_MASK 0x1F 430 #define UART_SCMR_SMARTCARD 0x20 431 #define UART_SCMR_2STOP_BIT 0x40 432 433 //both Transmitter empty / Transmit-hold-register empty 434 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 435 436 // UART_SEL_TYPE 437 #define UART_SEL_HK_R2 0x00 438 #define UART_SEL_VD_MHEG5 0x02 439 #define UART_SEL_TSP 0x03 440 #define UART_SEL_PIU_UART0 0x04 441 #define UART_SEL_PIU_UART1 0x05 442 #define UART_SEL_PIU_UART2 0x06 443 #define UART_SEL_PIU_FAST_UART 0x07 444 #define UART_SEL_DMD_MCU51_TXD0 0x08 445 #define UART_SEL_DMD_MCU51_TXD1 0x09 446 #define UART_SEL_VD_MCU51_TXD0 0x0A 447 #define UART_SEL_VD_MCU51_TXD1 0x0B 448 #define UART_SEL_AUDIO_R2 0x0C 449 #define UART_SEL_SECURE_R2 0x0D 450 #define UART_SEL_OFF 0x0F 451 452 // 453 // PM_SLEEP 454 // for UART RX enable and switch MCU & PM51 455 // 456 #define REG_PM_SLEEP 0x0E00 457 #define REG_PM_UART_CTRL (REG_PM_SLEEP + (0x09*2) + 1) 458 #define _uart_rx_enable BIT3 459 #define _reg_hk51_uart0_en BIT4 460 461 // 462 // CHIP_TOP 463 // for UART PAD Select 464 // 465 #define CHIP_REG_BASE 0x1E00 466 #define CHIP_REG_FastUART (CHIP_REG_BASE+ (0x02*2)) 467 #define CHIP_FastUART_PAD_1 (BIT4) 468 #define CHIP_FastUART_PAD_2 (BIT5) 469 #define CHIP_FastUART_PAD_3 (BIT4|BIT5) 470 #define CHIP_FastUART_PAD_MASK (BIT4|BIT5) 471 #define CHIP_REG_FourthUART (CHIP_REG_BASE+ (0x02*2)) 472 #define CHIP_FourthUART_PAD_1 (BIT6) 473 #define CHIP_FourthUART_PAD_2 (BIT7) 474 #define CHIP_FourthUART_PAD_3 (BIT6|BIT7) 475 #define CHIP_FourthUART_PAD_MASK (BIT6|BIT7) 476 #define CHIP_REG_SecondUART (CHIP_REG_BASE+ (0x02*2) + 1) 477 #define CHIP_SecondUART_PAD_1 (BIT0) 478 #define CHIP_SecondUART_PAD_2 (BIT1) 479 #define CHIP_SecondUART_PAD_3 (BIT0|BIT1) 480 #define CHIP_SecondUART_PAD_MASK (BIT0|BIT1) 481 #define CHIP_REG_ThirdUART (CHIP_REG_BASE+ (0x02*2) + 1) 482 #define CHIP_ThirdUART_PAD_1 (BIT2) 483 #define CHIP_ThirdUART_PAD_2 (BIT3) 484 #define CHIP_ThirdUART_PAD_3 (BIT2|BIT3) 485 #define CHIP_ThirdUART_PAD_MASK (BIT2|BIT3) 486 487 #define UART_CLOCK_REG_BASE (0xB00) 488 #define UART0_CLK_REG (UART_CLOCK_REG_BASE + 0x27) 489 #define UART1_CLK_REG (UART_CLOCK_REG_BASE + 0x28) 490 #define UART2_CLK_REG (UART_CLOCK_REG_BASE + 0x29) 491 #define FUART_CLK_REG (UART_CLOCK_REG_BASE + 0x2A) 492 493 //------------------------------------------------------------------------------------------------- 494 // Type and Structure 495 //------------------------------------------------------------------------------------------------- 496 497 #endif // _REG_UART_H_ 498