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Searched refs:TSIO1_BTRAIN_INT_CLR (Results 1 – 4 of 4) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/tsio/
H A DhalTSIO.c1698 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_BTRAIN_INT_CLR); in HAL_TSIO_Int_Bittraining_Clear()
1700 _REG16_CLR(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_BTRAIN_INT_CLR); in HAL_TSIO_Int_Bittraining_Clear()
1825 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_BTRAIN_INT_CLR); in HAL_TSIO_Analogphase_Init()
1827 _REG16_CLR(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_BTRAIN_INT_CLR); in HAL_TSIO_Analogphase_Init()
H A DregTSIO.h575 #define TSIO1_BTRAIN_INT_CLR 0x0200 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/tsio/
H A DhalTSIO.c1698 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_BTRAIN_INT_CLR); in HAL_TSIO_Int_Bittraining_Clear()
1700 _REG16_CLR(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_BTRAIN_INT_CLR); in HAL_TSIO_Int_Bittraining_Clear()
1825 _REG16_SET(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_BTRAIN_INT_CLR); in HAL_TSIO_Analogphase_Init()
1827 _REG16_CLR(&(_TSIOCtrl1->BTRAIN_CONFIG3), TSIO1_BTRAIN_INT_CLR); in HAL_TSIO_Analogphase_Init()
H A DregTSIO.h575 #define TSIO1_BTRAIN_INT_CLR 0x0200 macro