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Searched refs:REG_TSP1_BANK (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/dscmb/
H A DregDSCMB.h698 #define REG_TSP1_BANK 0x00B00UL //TSP1 0x1016 macro
699 #define REG_TSP_IDR_CTRL (REG_TSP1_BANK + 0x0048UL)
703 #define REG_TSP_IDR_ADDR_L (REG_TSP1_BANK + 0x0049UL)
704 #define REG_TSP_IDR_ADDR_H (REG_TSP1_BANK + 0x004aUL)
705 #define REG_TSP_IDR_WRITE_L (REG_TSP1_BANK + 0x004bUL)
706 #define REG_TSP_IDR_WRITE_H (REG_TSP1_BANK + 0x004cUL)
707 #define REG_TSP_IDR_READ_L (REG_TSP1_BANK + 0x004dUL)
708 #define REG_TSP_IDR_READ_H (REG_TSP1_BANK + 0x004eUL)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/dscmb/
H A DregDSCMB.h727 #define REG_TSP1_BANK 0x00B00UL //TSP1 0x1016 macro
728 #define REG_TSP_IDR_CTRL (REG_TSP1_BANK + 0x0048UL)
732 #define REG_TSP_IDR_ADDR_L (REG_TSP1_BANK + 0x0049UL)
733 #define REG_TSP_IDR_ADDR_H (REG_TSP1_BANK + 0x004aUL)
734 #define REG_TSP_IDR_WRITE_L (REG_TSP1_BANK + 0x004bUL)
735 #define REG_TSP_IDR_WRITE_H (REG_TSP1_BANK + 0x004cUL)
736 #define REG_TSP_IDR_READ_L (REG_TSP1_BANK + 0x004dUL)
737 #define REG_TSP_IDR_READ_H (REG_TSP1_BANK + 0x004eUL)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/dscmb/
H A DregDSCMB.h727 #define REG_TSP1_BANK 0x00B00UL //TSP1 0x1016 macro
728 #define REG_TSP_IDR_CTRL (REG_TSP1_BANK + 0x0048UL)
732 #define REG_TSP_IDR_ADDR_L (REG_TSP1_BANK + 0x0049UL)
733 #define REG_TSP_IDR_ADDR_H (REG_TSP1_BANK + 0x004aUL)
734 #define REG_TSP_IDR_WRITE_L (REG_TSP1_BANK + 0x004bUL)
735 #define REG_TSP_IDR_WRITE_H (REG_TSP1_BANK + 0x004cUL)
736 #define REG_TSP_IDR_READ_L (REG_TSP1_BANK + 0x004dUL)
737 #define REG_TSP_IDR_READ_H (REG_TSP1_BANK + 0x004eUL)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/dscmb/
H A DregDSCMB.h698 #define REG_TSP1_BANK 0x00B00UL //TSP1 0x1016 macro
699 #define REG_TSP_IDR_CTRL (REG_TSP1_BANK + 0x0048UL)
703 #define REG_TSP_IDR_ADDR_L (REG_TSP1_BANK + 0x0049UL)
704 #define REG_TSP_IDR_ADDR_H (REG_TSP1_BANK + 0x004aUL)
705 #define REG_TSP_IDR_WRITE_L (REG_TSP1_BANK + 0x004bUL)
706 #define REG_TSP_IDR_WRITE_H (REG_TSP1_BANK + 0x004cUL)
707 #define REG_TSP_IDR_READ_L (REG_TSP1_BANK + 0x004dUL)
708 #define REG_TSP_IDR_READ_H (REG_TSP1_BANK + 0x004eUL)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/dscmb/
H A DregDSCMB.h800 #define REG_TSP1_BANK 0x00B00UL //TSP1 0x1016 macro
801 #define REG_TSP_IDR_CTRL (REG_TSP1_BANK + 0x0048UL)
805 #define REG_TSP_IDR_ADDR_L (REG_TSP1_BANK + 0x0049UL)
806 #define REG_TSP_IDR_ADDR_H (REG_TSP1_BANK + 0x004aUL)
807 #define REG_TSP_IDR_WRITE_L (REG_TSP1_BANK + 0x004bUL)
808 #define REG_TSP_IDR_WRITE_H (REG_TSP1_BANK + 0x004cUL)
809 #define REG_TSP_IDR_READ_L (REG_TSP1_BANK + 0x004dUL)
810 #define REG_TSP_IDR_READ_H (REG_TSP1_BANK + 0x004eUL)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/mooney/dscmb/
H A DregDSCMB.h137 #define REG_TSP1_BANK 0x0B00UL macro
139 #define REG_TSP1_CACTRL (REG_TSP1_BANK+ 0x0040UL)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/messi/dscmb/
H A DregDSCMB.h137 #define REG_TSP1_BANK 0x0B00UL macro
139 #define REG_TSP1_CACTRL (REG_TSP1_BANK+ 0x0040UL)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/mainz/dscmb/
H A DregDSCMB.h137 #define REG_TSP1_BANK 0x0B00UL macro
139 #define REG_TSP1_CACTRL (REG_TSP1_BANK+ 0x0040UL)