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Searched refs:REG_SC_BKC6_C5 (Results 1 – 24 of 24) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A DMaserati_2D_4K2K.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
804 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_FHD_YUV()
805 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_FHD_YUV()
812 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_2D_4K2K_2D_FHD_YUV()
1225 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1226 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1233 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1646 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_4K2K_YUV()
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H A DMaserati_2D_FHD.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x04, 0x1f); // reg_col_height in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
804 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x04, 0x1f); // reg_col_height in MFC_3D_2D_FHD_2D_FHD_YUV()
805 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_FHD_2D_FHD_YUV()
812 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_ACT_4K0_5K.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K1K_LLRR_240.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A DMaserati_ACT_4K1K.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x40, 0x40); // reg_lineswap in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_60.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x40, 0x40); // reg_lineswap in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A Dhwreg_frc_map.h13363 #define REG_SC_BKC6_C5 (REG_SCALER_BASE+0xC6C5) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A DMaserati_2D_4K2K.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS()
804 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_FHD_YUV()
805 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_FHD_YUV()
812 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_2D_4K2K_2D_FHD_YUV()
1225 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1226 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1233 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS()
1646 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_2D_4K2K_2D_4K2K_YUV()
[all …]
H A DMaserati_2D_FHD.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x04, 0x1f); // reg_col_height in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_2D_FHD_2D_FHD_RGB_BYPASS()
804 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x04, 0x1f); // reg_col_height in MFC_3D_2D_FHD_2D_FHD_YUV()
805 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_2D_FHD_2D_FHD_YUV()
812 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_2D_FHD_2D_FHD_YUV()
H A DMaserati_ACT_4K1K.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_4K1K_ACT_3D_4K1K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K2K_120.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_FRC_ACT_4K2K_120_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K0_5K_LLRR_240.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_FRC_ACT_4K0_5K_LLRR_240_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_60.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x40, 0x40); // reg_lineswap in MFC_3D_FRC_PAS_4K2K_60_3D_FHD_TB()
H A DMaserati_FRC_ACT_4K1K_120.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_FRC_ACT_4K1K_120_3D_FHD_TB()
H A DMaserati_FRC_PAS_4K2K_120.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x40, 0x40); // reg_lineswap in MFC_3D_FRC_PAS_4K2K_120_3D_FHD_TB()
H A DMaserati_ACT_4K0_5K.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_4K0_5K_ACT_3D_4K0_5K_ACT_NO_FRC()
H A DMaserati_FRC_ACT_4K1K_LLRR_240.c383 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x08, 0x1f); // reg_col_height in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
384 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x60); // reg_lb_mode_control in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
391 MDrv_WriteByteMask( REG_SC_BKC6_C5, 0x00, 0x40); // reg_lineswap in MFC_3D_FRC_ACT_4K1K_LLRR_240_3D_FHD_TB()
H A Dhwreg_frc_map.h13363 #define REG_SC_BKC6_C5 (REG_SCALER_BASE+0xC6C5) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_frc_map.h11294 #define REG_SC_BKC6_C5 (REG_SCALER_BASE+0xC6C5) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_frc_map.h11294 #define REG_SC_BKC6_C5 (REG_SCALER_BASE+0xC6C5) macro