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Searched refs:REG_SC_BK12_67_L (Results 1 – 25 of 77) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_sc.c2108 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will… in Hal_SC_OP_Memory_Write_Request()
5121 … if(bPreFDMaskStatse != (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0)) in MHal_XC_DTVPatchISR()
5123 bPreFDMaskStatse =(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0); in MHal_XC_DTVPatchISR()
5135 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
5151 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_ip.c2316 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))) in HAL_SC_ip_Get_FD_Mask_Status()
2323 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(5))) in HAL_SC_ip_Get_FD_Mask_Status()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_ip.c2289 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))) in HAL_SC_ip_Get_FD_Mask_Status()
2296 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(5))) in HAL_SC_ip_Get_FD_Mask_Status()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_ip.c2289 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))) in HAL_SC_ip_Get_FD_Mask_Status()
2296 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(5))) in HAL_SC_ip_Get_FD_Mask_Status()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_ip.c2289 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))) in HAL_SC_ip_Get_FD_Mask_Status()
2296 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(5))) in HAL_SC_ip_Get_FD_Mask_Status()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_sc.c2234 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will… in Hal_SC_OP_Memory_Write_Request()
5257 … if(bPreFDMaskStatse != (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0)) in MHal_XC_DTVPatchISR()
5259 bPreFDMaskStatse =(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0); in MHal_XC_DTVPatchISR()
5271 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
5287 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_sc.c2850 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will… in Hal_SC_OP_Memory_Write_Request()
6371 … if(bPreFDMaskStatse != (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0)) in MHal_XC_DTVPatchISR()
6373 bPreFDMaskStatse =(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0); in MHal_XC_DTVPatchISR()
6385 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
6401 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_sc.c2979 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will… in Hal_SC_OP_Memory_Write_Request()
7094 … if(bPreFDMaskStatse != (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0)) in MHal_XC_DTVPatchISR()
7096 bPreFDMaskStatse =(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0); in MHal_XC_DTVPatchISR()
7108 Mhal_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
7124 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_sc.c3229 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will… in Hal_SC_OP_Memory_Write_Request()
7132 … if(bPreFDMaskStatse != (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0)) in MHal_XC_DTVPatchISR()
7134 bPreFDMaskStatse =(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0); in MHal_XC_DTVPatchISR()
7146 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
7162 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_sc.c3526 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will… in Hal_SC_OP_Memory_Write_Request()
7662 … if(bPreFDMaskStatse != (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0)) in MHal_XC_DTVPatchISR()
7664 bPreFDMaskStatse =(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0); in MHal_XC_DTVPatchISR()
7676 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
7692 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_sc.c3546 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will… in Hal_SC_OP_Memory_Write_Request()
7685 … if(bPreFDMaskStatse != (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0)) in MHal_XC_DTVPatchISR()
7687 bPreFDMaskStatse =(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0); in MHal_XC_DTVPatchISR()
7699 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
7715 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_sc.c3837 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will… in Hal_SC_OP_Memory_Write_Request()
7897 … if(bPreFDMaskStatse != (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0)) in MHal_XC_DTVPatchISR()
7899 bPreFDMaskStatse =(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0); in MHal_XC_DTVPatchISR()
7911 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
7927 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_sc.c3837 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will… in Hal_SC_OP_Memory_Write_Request()
7898 … if(bPreFDMaskStatse != (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0)) in MHal_XC_DTVPatchISR()
7900 bPreFDMaskStatse =(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0); in MHal_XC_DTVPatchISR()
7912 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
7928 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, 0x80 ,0xF0); in MHal_XC_DTVPatchISR()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_sc.c1497 …SC_W2BYTEMSK(0,REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will stop OPW and OP memory … in Hal_SC_OP_Memory_Write_Request()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_sc.c1517 …SC_W2BYTEMSK(0,REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will stop OPW and OP memory … in Hal_SC_OP_Memory_Write_Request()
/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/include/
H A DMooney_Main.c8817 { PQ_MAP_REG(REG_SC_BK12_67_L), 0x02, 0x00 },
/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/include/
H A DMaserati_Main.c11284 { PQ_MAP_REG(REG_SC_BK12_67_L), 0x02, 0x00 },
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/include/
H A DMaserati_Main.c15084 { PQ_MAP_REG(REG_SC_BK12_67_L), 0x02, 0x00 },
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/include/
H A DManhattan_Main.c10995 { PQ_MAP_REG(REG_SC_BK12_67_L), 0x02, 0x00 },
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h4226 #define REG_SC_BK12_67_L _PK_L_(0x12, 0x67) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h4226 #define REG_SC_BK12_67_L _PK_L_(0x12, 0x67) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h4228 #define REG_SC_BK12_67_L _PK_L_(0x12, 0x67) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h4228 #define REG_SC_BK12_67_L _PK_L_(0x12, 0x67) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h4228 #define REG_SC_BK12_67_L _PK_L_(0x12, 0x67) macro
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/include/
H A DMaxim_Main.c15056 { PQ_MAP_REG(REG_SC_BK12_67_L), 0x02, 0x00 },

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