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Searched refs:REG_SC_BK11_18_L (Results 1 – 25 of 63) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_sc.c1128 …MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_18_L, ((gSrcInfo[MAIN_WINDOW].Status2.u16PreVCusScal… in _Hal_SC_fill_main_sw_db_burst()
1134 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_18_L, 0, 0x9FFF); in _Hal_SC_fill_main_sw_db_burst()
1532 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_18_L, ((gSrcInfo[MAIN_WINDOW].Status2.u16PreVCu… in Hal_SC_sw_db()
1538 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_18_L, 0, 0x9FFF); in Hal_SC_sw_db()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_sc.c1349 …MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_18_L, ((gSrcInfo[MAIN_WINDOW].Status2.u16PreVCusScal… in _Hal_SC_fill_main_sw_db_burst()
1355 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_18_L, 0, 0x9FFF); in _Hal_SC_fill_main_sw_db_burst()
1731 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_18_L,(u32_FrameBuffer_Linelimit)|BIT(15), 0x9FF… in Hal_SC_sw_db()
1737 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_18_L, 0, 0x9FFF); in Hal_SC_sw_db()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_sc.c5975 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, bEnable? BIT(15):0, BIT(15)); in MHal_SC_set_manual_rbank_switch_cnt()
5979 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, u16SwitchCnt, 0x1FFF); in MHal_SC_set_manual_rbank_switch_cnt()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_sc.c6112 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, bEnable? BIT(15):0, BIT(15)); in MHal_SC_set_manual_rbank_switch_cnt()
6116 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, u16SwitchCnt, 0x1FFF); in MHal_SC_set_manual_rbank_switch_cnt()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_sc.c7215 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, bEnable? BIT(15):0, BIT(15)); in MHal_SC_set_manual_rbank_switch_cnt()
7219 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, u16SwitchCnt, 0x1FFF); in MHal_SC_set_manual_rbank_switch_cnt()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_sc.c7822 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, bEnable? BIT(15):0, BIT(15)); in MHal_SC_set_manual_rbank_switch_cnt()
7826 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, u16SwitchCnt, 0x1FFF); in MHal_SC_set_manual_rbank_switch_cnt()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_sc.c8026 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, bEnable? BIT(15):0, BIT(15)); in MHal_SC_set_manual_rbank_switch_cnt()
8030 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, u16SwitchCnt, 0x1FFF); in MHal_SC_set_manual_rbank_switch_cnt()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_sc.c8723 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, bEnable? BIT(15):0, BIT(15)); in MHal_SC_set_manual_rbank_switch_cnt()
8727 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, u16SwitchCnt, 0x1FFF); in MHal_SC_set_manual_rbank_switch_cnt()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_sc.c8746 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, bEnable? BIT(15):0, BIT(15)); in MHal_SC_set_manual_rbank_switch_cnt()
8750 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, u16SwitchCnt, 0x1FFF); in MHal_SC_set_manual_rbank_switch_cnt()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_sc.c9004 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, bEnable? BIT(15):0, BIT(15)); in MHal_SC_set_manual_rbank_switch_cnt()
9008 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, u16SwitchCnt, 0x1FFF); in MHal_SC_set_manual_rbank_switch_cnt()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_sc.c9005 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, bEnable? BIT(15):0, BIT(15)); in MHal_SC_set_manual_rbank_switch_cnt()
9009 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, u16SwitchCnt, 0x1FFF); in MHal_SC_set_manual_rbank_switch_cnt()
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h3806 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h3806 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h3808 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h3808 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h3808 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dhwreg_wble.h3806 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A Dhwreg_dlc.h3808 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/include/
H A Dhwreg_ace.h3806 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A Dhwreg_dlc.h3808 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/include/
H A Dhwreg_ace.h3806 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/messi/dlc/include/
H A Dhwreg_dlc.h3808 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/messi/wble/include/
H A Dhwreg_wble.h3806 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/M7821/wble/include/
H A Dhwreg_wble.h3806 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/ace/include/
H A Dhwreg_ace.h3806 #define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) macro

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