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Searched refs:REG_SC_BK03_2F_L (Results 1 – 25 of 77) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_ip.c1059 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, bEnable<<4, BIT(4) ); // SW patch for HD… in Hal_SC_ip_set_de_only_mode()
1134 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2227 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_ip.c1106 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, bEnable<<4, BIT(4) ); // SW patch for HD… in Hal_SC_ip_set_de_only_mode()
1181 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2221 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_ip.c1059 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, bEnable<<4, BIT(4) ); // SW patch for HD… in Hal_SC_ip_set_de_only_mode()
1134 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2214 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_ip.c1059 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, bEnable<<4, BIT(4) ); // SW patch for HD… in Hal_SC_ip_set_de_only_mode()
1134 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2214 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_ip.c1063 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, bEnable<<4, BIT(4) ); // SW patch for HD… in Hal_SC_ip_set_de_only_mode()
1138 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2216 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_ip.c1062 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, bEnable<<4, BIT(4) ); // SW patch for HD… in Hal_SC_ip_set_de_only_mode()
1137 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2187 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
H A Dmhal_sc.c351 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (benable ? BIT(4):0), BIT(4)); // SW patc… in Hal_SC_de_only_en()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_ip.c1063 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, bEnable<<4, BIT(4) ); // SW patch for HD… in Hal_SC_ip_set_de_only_mode()
1138 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2216 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_ip.c1062 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, bEnable<<4, BIT(4) ); // SW patch for HD… in Hal_SC_ip_set_de_only_mode()
1137 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2187 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
H A Dmhal_sc.c272 …SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (benable ? BIT(4):0), BIT(4)); // SW patc… in Hal_SC_de_only_en()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_ip.c1059 …SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, bEnable<<4, BIT(4) ); // SW patch for HD… in Hal_SC_ip_set_de_only_mode()
1134 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2227 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_ip.c1021 SC_W2BYTEMSK(0, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
1796 SC_W2BYTE(0,REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_ip.c1021 SC_W2BYTEMSK(0, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
1796 SC_W2BYTE(0,REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_ip.c1001 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2096 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_ip.c1001 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2095 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_ip.c1001 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2095 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_ip.c1001 SC_W2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (bEnable<<15), BIT(15) ); in Hal_SC_ip_set_de_bypass_mode()
2095 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, value); in HAL_SC_ip_3DMainSub_IPSync()
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/
H A Dmdrv_sc_ip.c466 … return ((SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, BIT(15) ))? TRUE : FALSE); in MDrv_SC_Get_DE_Bypass_Mode()
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h986 #define REG_SC_BK03_2F_L _PK_L_(0x03, 0x2F) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h986 #define REG_SC_BK03_2F_L _PK_L_(0x03, 0x2F) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h988 #define REG_SC_BK03_2F_L _PK_L_(0x03, 0x2F) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h986 #define REG_SC_BK03_2F_L _PK_L_(0x03, 0x2F) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h988 #define REG_SC_BK03_2F_L _PK_L_(0x03, 0x2F) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dhwreg_wble.h986 #define REG_SC_BK03_2F_L _PK_L_(0x03, 0x2F) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A Dhwreg_dlc.h988 #define REG_SC_BK03_2F_L _PK_L_(0x03, 0x2F) macro

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