Home
last modified time | relevance | path

Searched refs:REG_SC_BK01_48_L (Results 1 – 25 of 67) sorted by relevance

123

/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_ip.c1944 SC_W2BYTEMSK(0,REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
1960 SC_W2BYTEMSK(0,REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
1976 SC_W2BYTEMSK(0,REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
1992 SC_W2BYTEMSK(0,REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2008 SC_W2BYTEMSK(0,REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2024 SC_W2BYTEMSK(0,REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_ip.c1944 SC_W2BYTEMSK(0,REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
1960 SC_W2BYTEMSK(0,REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
1976 SC_W2BYTEMSK(0,REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
1992 SC_W2BYTEMSK(0,REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2008 SC_W2BYTEMSK(0,REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2024 SC_W2BYTEMSK(0,REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_ip.c2350 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2368 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2386 … SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2404 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2422 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2440 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_ip.c2430 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2446 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2462 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2478 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2494 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2510 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_ip.c2410 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2426 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2442 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2458 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2474 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2490 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_ip.c2417 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2433 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2449 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2465 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2481 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2497 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_ip.c2408 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2424 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2440 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2456 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2472 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2488 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_ip.c2419 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2435 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2451 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2467 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2483 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2499 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_ip.c2323 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2341 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2359 … SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2377 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2395 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2413 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_ip.c2323 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2341 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2359 … SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2377 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2395 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2413 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_ip.c2376 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2392 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2408 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2424 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2440 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2456 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_ip.c2323 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2341 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2359 … SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2377 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2395 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2413 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_ip.c2405 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2421 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2437 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2453 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2469 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2485 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_ip.c2376 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2392 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2408 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2424 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2440 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2456 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_ip.c2430 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 6, BIT(6)); in HAL_SC_ip_set_hv_sync_status_check()
2446 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable, BIT(0)); in HAL_SC_ip_set_new_mode_interlaced_detect()
2462 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, (u8Source & 0x3) << 1, BIT(2)|BIT(1)); in HAL_SC_ip_set_hv_sync_source_select()
2478 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bEnable << 3, BIT(3)); in HAL_SC_ip_set_vtotal_count_by_pixel_clock()
2494 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 4, BIT(4)); in HAL_SC_ip_set_vsync_invert()
2510 SC_W2BYTEMSK(0, REG_SC_BK01_48_L, bInvert << 5, BIT(5)); in HAL_SC_ip_set_hsync_invert()
/utopia/UTPA2-700.0.x/modules/wble/hal/manhattan/wble/include/
H A Dhwreg_wble.h514 #define REG_SC_BK01_48_L _PK_L_(0x01, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/ace/include/
H A Dhwreg_ace.h514 #define REG_SC_BK01_48_L _PK_L_(0x01, 0x48) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/k6/dlc/include/
H A Dhwreg_dlc.h516 #define REG_SC_BK01_48_L _PK_L_(0x01, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/ace/include/
H A Dhwreg_ace.h514 #define REG_SC_BK01_48_L _PK_L_(0x01, 0x48) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/manhattan/dlc/include/
H A Dhwreg_dlc.h516 #define REG_SC_BK01_48_L _PK_L_(0x01, 0x48) macro
/utopia/UTPA2-700.0.x/modules/wble/hal/macan/wble/include/
H A Dhwreg_wble.h514 #define REG_SC_BK01_48_L _PK_L_(0x01, 0x48) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/curry/dlc/include/
H A Dhwreg_dlc.h516 #define REG_SC_BK01_48_L _PK_L_(0x01, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/ace/include/
H A Dhwreg_ace.h514 #define REG_SC_BK01_48_L _PK_L_(0x01, 0x48) macro
/utopia/UTPA2-700.0.x/modules/dlc/hal/M7821/dlc/include/
H A Dhwreg_dlc.h516 #define REG_SC_BK01_48_L _PK_L_(0x01, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/ace/include/
H A Dhwreg_ace.h514 #define REG_SC_BK01_48_L _PK_L_(0x01, 0x48) macro

123